Self-aligned Carbon Electronics Embedded Gate Electrode
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Solution Overview
Problem
The semiconductor industry faces challenges with adhesion issues between carbon-based materials and high dielectric constant insulation materials, as well as alignment problems in transistor designs, which hinder the reduction of node sizes in future device designs.
Innovation Solution
A method involving the formation of a buried gate electrode in a dielectric substrate, patterning a stack of high dielectric constant, carbon-based, and protection layers, and etching to create self-aligned source and drain regions by depositing conductive material in cavities exposed on opposite sides of the gate electrode, ensuring correct alignment and improved adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If carbon-based materials are used in transistor devices, then high-performance switching is achieved, but adhesion issues occur between carbon material and high-k insulation materials
Solution Approach 1:
An intermediate layer is introduced between the carbon-based material and the high-k dielectric material to serve as a bonding interface. This intermediate layer facilitates adhesion between the two materials that would otherwise be incompatible, resolving the adhesion issues while maintaining the high-performance switching characteristics of the carbon-based transistor device.
2Manufacturing precision
If conventional alignment methods are used in transistor fabrication, then manufacturing processes are simple, but alignment precision deteriorates at smaller node sizes
Solution Approach 1:
The fabrication method employs self-aligned processes where previously deposited structures serve as alignment references for subsequent steps. Specifically, the high-k dielectric layer and carbon-based material are deposited and patterned in a sequence where each layer automatically aligns with the previous one, eliminating the need for separate alignment operations and maintaining high alignment precision even at reduced node sizes.
3Productivity
If node sizes are reduced to improve device density, then productivity increases, but alignment issues worsen and act as a barrier to further scaling
Solution Approach 1:
The self-aligned fabrication approach allows continuous scaling to smaller node sizes because each deposition and patterning step automatically references the previous structure, maintaining alignment precision independent of the absolute feature size. This enables higher device density without being constrained by alignment difficulties that typically arise at smaller dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and scalability of transistor designs by improving the interface between high-dielectric constant materials and carbon-based field-effect materials, enabling correct alignment of source and drain regions relative to the gate structure, thus supporting smaller device sizes and improved performance.
Implementation Method 1
employing atomic layer deposition to form the conductive material in contact with the carbon-based semi-conducting layer
Data Source
AI summary
A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.