3D-IC Package Thermal Management via Carbon Interposer
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Solution Overview
Problem
Current 3D-IC technologies face challenges in achieving high device and I/O density, reduced power consumption, and improved access times within a compact form factor, particularly in heat dissipation and interconnect routing, due to the limitations of traditional substrate via (TSV) technology.
Innovation Solution
The method involves forming vias in a substrate and attaching microelectronic elements with connecting elements that extend beyond the microelectronic elements, utilizing carbon materials for enhanced thermal conductivity in the encapsulation and connecting elements to improve heat dissipation and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional TSV technology is used for vertical stacking, then device density and functionality are improved, but heat dissipation and interconnect routing challenges worsen
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary layer between stacked microelectronic elements. This interposer provides dedicated TSV structures and thermal management pathways that mediate the heat transfer and electrical interconnection, separating the heat generation at the device level from the heat dissipation at the package level, thereby resolving the heat dissipation challenges while maintaining high device density
Solution Approach 2:
The patent employs composite material structures in the interposer and encapsulation layers, combining materials with different thermal and electrical properties. This includes using thermally conductive materials in specific regions to enhance heat dissipation while maintaining electrical insulation where needed, thus addressing both heat management and electrical interconnect requirements simultaneously
2Quantity of substance
If more microelectronic elements are stacked vertically, then I/O density is improved, but thermal management difficulties increase
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional thermal management by implementing thermal vias and heat spreaders that conduct heat vertically through the stacked structure. This dimensional approach to thermal management allows heat to be dissipated through multiple pathways in the vertical dimension, effectively managing thermal loads from high-density stacked elements
Solution Approach 2:
The interposer substrate serves multiple functions simultaneously: it provides electrical interconnection between stacked elements, establishes thermal management pathways, and offers mechanical support for the high-density stack. This multi-functionality allows the same structural element to address both I/O density and thermal management requirements without adding separate dedicated components
3Volume of moving object
If compact design is maintained, then form factor is reduced, but heat dissipation becomes more difficult
Solution Approach 1:
The patent implements a nested structure where thermal management components are integrated within the compact package volume. Heat spreaders, thermal vias, and thermal interface materials are nested between and around the stacked microelectronic elements, utilizing the existing vertical space for dual purposes of electrical interconnection and thermal conduction, thereby maintaining compact form factor while enhancing heat dissipation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher density I/O configurations and improved thermal management, enhancing the performance and efficiency of 3D-IC systems by maintaining a compact design while addressing heat dissipation and interconnect challenges.
Implementation Method 1
the encapsulation layer comprises a carbon material dispersed therein to increase thermal conductivity of the encapsulation layer
Implementation Method 2
at least one of the one or more connecting elements comprises a carbon material to increase thermal conductivity of the at least one of the one or more connecting elements
Data Source
AI summary
A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.