Carbon-Based Memory Interconnects for Low-RC Resistive Arrays
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Solution Overview
Problem
Resistive memory devices face increased RC delay and high resistivity with scaling due to the limitations of metallic nitride liners and fill materials, which cannot be reduced in thickness, affecting the performance of metal lines.
Innovation Solution
The use of carbon-based conductor lines, such as graphene nanoribbons or carbon nanotubes, reduces the thickness of bit lines and eliminates the need for barrier layers like TiN/TaN, while maintaining low resistivity through hexagonal carbon arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metallic nitride liner and metallic fill material are used in metal lines, then adhesion and diffusion barrier functions are provided, but line resistance increases with scaling due to minimum thickness constraints
Solution Approach 1:
The patent extracts and eliminates the metallic nitride liner layer from the interconnect structure, replacing it with a carbon-based conductor that inherently provides both conduction and barrier functions without requiring a separate liner layer. This removal of the liner layer reduces the overall line resistance while maintaining necessary adhesion and diffusion barrier properties through the carbon-based material's inherent characteristics.
Solution Approach 2:
The patent changes the material parameter from metallic nitride to carbon-based conductor, fundamentally altering the electrical resistance parameter. The carbon-based material enables thinner line dimensions with lower resistance compared to conventional metallic fill materials, directly addressing the resistance increase problem caused by scaling while maintaining the required barrier functions.
2Object-affected harmful factors
If metallic nitride liner thickness is reduced during scaling, then line resistance decreases, but adhesion and diffusion barrier functions are compromised
Solution Approach 1:
The carbon-based conductor material performs multiple functions simultaneously: it provides electrical conduction, adhesion to underlying layers, and diffusion barrier properties. This multi-functionality eliminates the need for a separate metallic nitride liner layer, allowing the conductor to be scaled down in thickness without compromising adhesion or barrier functions, thereby reducing line resistance while maintaining reliability.
Solution Approach 2:
The patent removes the metallic nitride liner layer entirely, extracting its barrier and adhesion functions and integrating them into the carbon-based conductor material itself. This extraction allows for reduced line thickness and lower resistance while maintaining the necessary protective and adhesive functions through the inherent properties of the carbon-based material.
3Productivity
If conventional metal lines are scaled down, then device density increases, but RC delay increases due to higher resistance
Solution Approach 1:
The patent changes the conductor material parameter from conventional metal to carbon-based material, which fundamentally alters the resistance parameter. The carbon-based conductor maintains lower resistance even at scaled-down dimensions, enabling increased device density without the associated increase in RC delay that plagues conventional metal interconnects.
Solution Approach 2:
The patent employs carbon-based conductor material that combines the benefits of low resistance with the ability to be scaled to thin dimensions. This composite approach (carbon-based material integrated with dielectric and other interconnect layers) achieves both high device density through scaling and low RC delay through the material's inherent electrical properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the thickness of bit lines and word lines, reducing RC delay and parasitic capacitance, enhancing the conductivity and thermal stability of resistive memory devices.
Implementation Method 1
maintaining low resistivity through hexagonal carbon arrangements
Implementation Method 2
reducing RC delay and parasitic capacitance
Data Source
AI summary
An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.