Carbon Patterns for Semiconductor Memory Polishing Uniformity
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Solution Overview
Problem
Existing semiconductor memory fabrication methods face challenges in ensuring uniformity and precision of variable resistance elements, leading to inconsistent electrical characteristics and difficulties in subsequent processing due to inadequate polishing techniques, which result in height differences between regions.
Innovation Solution
The implementation of a semiconductor memory device with a cross-point structure and the use of conductive carbon-containing patterns and insulating carbon-containing patterns to improve polishing margins, ensure uniformity of memory cell heights, and reduce thermal interference between stacked structures, utilizing materials like graphite, carbon nanotubes, SiC, and DLC for the conductive and insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional polishing techniques are used, then the fabrication process is simple, but height differences between regions occur and uniformity of memory cell heights deteriorates
Solution Approach 1:
An insulating carbon-containing pattern is introduced as an intermediary layer between the variable resistance elements and the polishing surface. This mediator layer protects the memory cell components during polishing, preventing excessive removal and height variations, thereby achieving uniform memory cell heights while maintaining a manageable fabrication process
Solution Approach 2:
The insulating carbon-containing pattern is formed in advance before the polishing step. This preliminary action ensures that the protective layer is already in place to prevent loss of memory cell components during subsequent polishing operations, achieving uniform heights without requiring complex real-time control
2Object-affected harmful factors
If conventional interlayer insulating structures are used, then the structure is simple, but thermal interference between stacked structures occurs
Solution Approach 1:
The interlayer insulating structure is constructed using composite materials including insulating carbon-containing patterns (such as DLC or amorphous carbon) combined with conventional insulating materials. This composite structure provides both electrical insulation and thermal isolation, reducing thermal interference between stacked memory structures while maintaining reasonable structural complexity
3Reliability
If standard conductive patterns are used, then the material selection is limited, but electrical characteristics and conductivity may be insufficient
Solution Approach 1:
The conductive carbon-containing patterns utilize variations in carbon material parameters such as crystallinity, orientation, and doping levels to achieve desired electrical characteristics. By adjusting these parameters, consistent electrical performance is achieved across different memory cells while allowing flexibility in material selection including graphite, carbon nanotubes, and amorphous carbon
Data Source
AI summary
An electronic device is provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate including a first region in which a plurality of memory cells are disposed and a second region adjacent to the first region; a first interlayer insulating layer disposed over the substrate; a plurality of first memory cells penetrating through the first interlayer insulating layer in the first region, an uppermost portion of each memory cell of the first memory cells having a first conductive carbon-containing pattern; and a first insulating carbon-containing pattern located over the first interlayer insulating layer in the second region.