Carbon-Rich STI Oxide Formation for Etch-Resistant Fin Trenches
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, the formation of high-quality carbon-rich dielectric layers for shallow trench isolation (STI) regions becomes challenging due to increased sensitivity to etching processes and the need for precise thermal budget control, especially in advanced technology nodes with high aspect ratio trenches.
Innovation Solution
A method involving the conformal deposition of a carbon-rich dielectric layer over semiconductor fins, followed by an anneal process to convert it into a carbon-rich oxide layer with an atomic percentage concentration of carbon between 0.5% and 4%, which is highly resistant to etching and allows for lower anneal temperatures, ensuring uniformity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric layers are used for STI regions in miniaturized semiconductor devices, then manufacturing is simpler, but etching resistance is insufficient and thermal budget control is compromised
Solution Approach 1:
The patent employs a composite dielectric layer structure consisting of a carbon-rich dielectric layer (with 1-30% carbon content) combined with conventional dielectric materials. This composite structure provides enhanced etching resistance while maintaining compatibility with existing manufacturing processes, thereby improving reliability without significantly increasing device complexity
Solution Approach 2:
The patent modifies the chemical composition parameters of the dielectric layer by incorporating carbon-rich materials with specific carbon content ranges (1-30%). This parameter change enhances etching resistance and enables better thermal budget control during fabrication, directly addressing the reliability improvement needed for miniaturized devices
2Reliability
If higher anneal temperatures are used to form carbon-rich oxide layers, then etching resistance improves, but thermal budget control is lost and uniformity deteriorates
Solution Approach 1:
The patent changes the chemical composition of the dielectric layer by incorporating carbon-rich materials, which fundamentally alters the annealing behavior. This allows the formation of carbon-rich oxide layers with high etching resistance at lower anneal temperatures (below 400°C), thereby maintaining thermal budget control and ensuring uniformity across the wafer
3Reliability
If carbon-rich dielectric layers are deposited conformally, then etching resistance and thermal budget control improve, but manufacturing complexity increases
Solution Approach 1:
The patent modifies the deposition process parameters to achieve conformal deposition of carbon-rich dielectric layers. By adjusting deposition conditions and material composition, the process achieves the desired conformal coverage with enhanced thermal budget control, balancing the improvement in reliability against the increase in manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a high-quality carbon-rich oxide layer that effectively resists etching processes, such as those using hydrofluoric acid, while enabling thermal budget control and improved uniformity even in high aspect ratio trenches, enhancing device performance and integration density.
Implementation Method 1
an anneal process to convert it into a carbon-rich oxide layer
Data Source
AI summary
A method includes etching a first trench in a semiconductor substrate to form a first fin and a second fin, and forming a shallow trench isolation (STI) region in the first trench, where forming the STI region includes depositing a first dielectric layer over top surfaces of the first fin and the second fin, and on sidewalls and a bottom surface of the first trench, the first dielectric layer including carbon, depositing a second dielectric layer over the first dielectric layer, and in the first trench, where the second dielectric layer fills the first trench, and performing an anneal process, where the anneal process releases carbon from the first dielectric layer into the second dielectric layer.