Card Controller Binary Mode for NAND Flash Update Speed
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Solution Overview
Problem
NAND flash memories require data to be written in memory block units, leading to inefficient data updates due to the inability to overwrite data, necessitating the use of a cache and subsequent data copying, which prolongs the data update process.
Innovation Solution
A card controller and memory card system that utilizes a binary mode for writing data to memory blocks holding management information, allowing data to be updated more efficiently by writing only to the lower bit of 2-bit memory cells, reducing the number of pages and time required for data updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written to NAND flash memory in memory block units, then data can be stored nonvolatilY, but data update time increases due to the inability to overwrite and the need for cache copying
Solution Approach 1:
The patent segments the 2-bit memory cell data into upper bit and lower bit components. The lower bit is written to all memory blocks uniformly, while the upper bit is written selectively based on validity flags. This segmentation allows partial data updates without requiring complete memory block rewriting, thereby reducing data update time while maintaining nonvolatile storage reliability.
Solution Approach 2:
The patent performs preliminary actions by setting validity flags (S1-S4) before writing upper bit data to specific memory blocks. This preliminary marking of valid data blocks allows the system to efficiently determine which blocks require upper bit updates, avoiding unnecessary writing operations and reducing overall data update time while preserving data integrity.
2Adaptability or versatility
If cache is used to write small amounts of data, then data can be updated, but the process requires copying data in memory block units which prolongs update time
Solution Approach 1:
The patent segments the data update process into two independent parts: lower bit writing (applied to all blocks) and upper bit writing (applied selectively to specific blocks based on validity flags). This eliminates the need for traditional cache copying operations, as updates can be applied directly to the target memory blocks in a segmented manner, significantly reducing update time while maintaining full data update capability.
Solution Approach 2:
The patent applies partial action by writing the upper bit only to memory blocks that actually require updates (identified by validity flags), rather than copying data to entire memory blocks. This partial updating approach maintains data update capability while minimizing the scope of writing operations, thereby reducing overall update time.
3Quantity of substance
If 2-bit memory cells are used to increase storage capacity, then memory density improves, but the complexity of data management increases due to multi-bit writing requirements
Solution Approach 1:
The patent segments the 2-bit data into upper and lower bits with independent writing mechanisms. The lower bit is written uniformly to all blocks, while the upper bit is written selectively based on validity flags. This segmentation simplifies data management complexity by providing clear rules for when and how to write each bit, making the multi-bit writing process more manageable despite increased storage capacity.
Solution Approach 2:
The patent changes the state parameters of memory blocks by setting validity flags (S1-S4) that indicate whether upper bit data should be written. This parameter change approach transforms the complex decision-making process into a simple flag-checking mechanism, reducing data management complexity while enabling efficient 2-bit memory cell utilization for increased storage capacity.
Data Source
AI summary
A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.