Carrier Aggregation Circuit Frequency Offset Compensation

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Solution Overview

Problem

Current Carrier Aggregation (CA) schemes in LTE mobile communication systems face challenges in properly compensating frequency offsets, leading to decreased transmission/reception performance, especially in inter-band or intra-band non-contiguous bandwidth scenarios, as they operate with signals from different timing points and frequency offsets.

Innovation Solution

A circuit and apparatus that utilize multiple CC processors to estimate and compensate frequency offsets, a reference clock generator to produce a reference clock, and PLL units to generate carrier frequencies, enabling effective frequency offset compensation across multiple Component Carriers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple CCs with different frequency offsets and timing points are aggregated, then data rate is increased, but frequency offset compensation becomes inaccurate leading to decreased transmission/reception performance

Engineering Contradiction:
Improvedata rateVSAvoidtransmission/reception performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the frequency offset compensation process into separate handling for each Component Carrier. Each CC processor independently estimates and compensates frequency offsets for its assigned CC, rather than using a unified compensation approach. This segmentation allows accurate compensation despite different frequency offsets and timing points across multiple CCs, resolving the contradiction between maintaining high data rate through CA and ensuring reliable transmission/reception performance.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If inter-band or intra-band non-contiguous CA schemes are used, then frequency usage fairness is improved, but frequency offset changes make proper compensation impossible

Engineering Contradiction:
Improvefrequency usage fairnessVSAvoidfrequency offset compensation accuracy
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements dynamic frequency offset compensation where each CC processor continuously estimates frequency offsets and adjusts compensation in real-time based on changing conditions. The system adapts to frequency offset changes that occur in inter-band and intra-band non-contiguous CA scenarios by updating compensation parameters dynamically, thereby maintaining reliable transmission/reception performance while enabling flexible frequency usage across different bands.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If signals from different timing points and frequency offsets are processed together, then carrier aggregation capability is enhanced, but transmission/reception performance decreases due to inability to properly compensate frequency offset

Engineering Contradiction:
Improvecarrier aggregation capabilityVSAvoidfrequency offset compensation precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by tailoring the frequency offset compensation approach to each specific Component Carrier's characteristics. Each CC processor is configured to handle the specific frequency offset and timing point of its assigned CC, applying localized compensation parameters rather than a global approach. This enables the system to process signals from different timing points and frequency offsets with the precision needed for each individual carrier, maintaining both CA capability and compensation accuracy.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUSRE49805E1Apparatus and circuit for processing carrier aggregation
Publication Date: 2024.01.16 SAMSUNG ELECTRONICS CO LTD
  • USRE49805E1 patent drawing
  • USRE49805E1 patent drawing
  • USRE49805E1 patent drawing

AI summary

A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.