Semiconductor Cell Structure With Carrier Barrier Trenches
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Solution Overview
Problem
The manufacturing process of power semiconductor devices using deep and shallow trenches is challenging due to stringent requirements for doping concentrations and trench dimensions, leading to potential functional deviations and difficulties in miniaturization, especially when trench etching errors occur, resulting in poor conduction paths and increased on-state voltage drops.
Innovation Solution
A cell structure for semiconductor devices is designed with a semiconductor substrate, trench units, carrier barrier regions, source-body regions, and metal layers, where the carrier barrier region has a higher doping concentration than the substrate, and an electric field shielding structure is used to limit conduction paths and enhance voltage handling, while allowing for adjustments in trench design to mitigate etching errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trenches and shallow trenches are used in combination to improve robustness and current density, then device performance is improved, but manufacturing precision requirements become more stringent
Solution Approach 1:
The device structure is segmented into multiple trench units (deep trenches and shallow trenches) with different functions. The deep trenches provide robustness and current density improvement, while the shallow trenches serve as etching reference markers. This segmentation allows each trench type to be optimized independently, reducing the interdependence that causes manufacturing precision issues.
Solution Approach 2:
The shallow trenches act as intermediary reference structures that facilitate the manufacturing process. By providing visible etching reference markers, they enable better alignment and depth control for the deep trenches, indirectly improving the precision of the critical deep trench structures without requiring direct measurement of each deep trench.
2Reliability
If the number of trenches is increased to improve device function, then device performance is improved, but device miniaturization becomes more difficult
Solution Approach 1:
The trench structure is divided into functionally distinct segments: deep trenches for performance enhancement and shallow trenches for process control. This segmentation reduces the need for numerous identical trenches, as the shallow trenches provide reference functionality that simplifies the overall arrangement and enables better spacing control.
Solution Approach 2:
The shallow trenches serve multiple functions: they act as etching reference markers, provide alignment references, and contribute to overall device structure. This multi-functionality reduces the need for separate dedicated reference structures, simplifying the overall device design and enabling miniaturization.
3Manufacturing precision
If trench etching window is misregistered, then doping concentration deviates from requirements, but process robustness should be maintained
Solution Approach 1:
The shallow trenches are formed first to establish reference markers before the deep trench etching process. This preliminary action creates visible references that guide subsequent etching and doping steps, enabling better registration and reducing the impact of misalignment on final device performance.
Solution Approach 2:
The shallow trenches provide visual feedback during the etching process, allowing operators to monitor and adjust the etching window registration in real-time. This feedback mechanism enables correction of alignment issues before they result in significant doping concentration deviations or conduction path defects.
Data Source
AI summary
A cell structure and a semiconductor device using the same. The cell structure comprises a semiconductor substrate; a plurality of slot units are provided at the top end of the semiconductor substrate; a corresponding carrier barrier region is provided at the bottom of each slot unit; a conductive material is provided in each slot; source body regions are provided between the adjacent slot units; one or more source regions are closely attached on the surface of each source body region, and the source regions and the source body regions are in contact with a first metal layer at the top of the semiconductor substrate; a first semiconductor region and a second metal layer in contact with the first semiconductor region are provided at the bottom of the semiconductor substrate.