Carrier Detect Synchronization for DC Offset Correction in DCRs
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Solution Overview
Problem
Direct Conversion Receivers (DCRs) suffer from baseband DC offset errors due to LO signal leakage and interference from adjacent channels, leading to distortion and reduced performance in detecting on-channel RF signals, especially at weak signal power levels.
Innovation Solution
A receiver system with mixed-mode analog and digital DC offset correction (DCOC) and autonomous carrier detect (CD) processing, utilizing a CD state machine and DCOC sequence manager to synchronize training sequences and correct DC offset errors, ensuring proper processing of RF signals and minimizing distortion artifacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If Direct Conversion Receiver (DCR) architecture is used to eliminate intermediate frequency stages, then device complexity is reduced, but baseband DC offset errors increase due to LO signal leakage and adjacent channel interference
Solution Approach 1:
The patent extracts and removes the harmful DC offset components from the baseband signal through dedicated DC offset correction circuits. These circuits separately process I and Q channel signals to eliminate DC offsets caused by LO leakage, thereby resolving the contradiction between simplified DCR structure and DC offset errors.
Solution Approach 2:
The patent introduces intermediary DC offset correction blocks as mediators between the mixer output and subsequent processing stages. These correction circuits act as intermediaries that compensate for DC offset errors without requiring changes to the overall DCR architecture, thus maintaining structural simplicity while eliminating harmful effects.
2Speed
If Carrier Detect (CD) processing is performed autonomously without synchronization, then processing speed is improved, but detection accuracy deteriorates due to DC offset distortion at weak signal levels
Solution Approach 1:
The patent applies preliminary DC offset correction to the I and Q channel signals before they are fed to the Carrier Detect processing block. By pre-correcting the DC offsets in advance, the CD processing can operate autonomously and quickly without being affected by distortion artifacts, thus maintaining both high speed and high detection accuracy.
Solution Approach 2:
The patent implements feedback mechanisms where the CD processing block monitors signal conditions and provides control signals back to the DC offset correction circuits. This feedback loop allows the system to dynamically adjust correction parameters based on actual signal conditions, ensuring accurate detection even at weak signal levels while maintaining autonomous operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively minimizes DC offset errors and distortion, enabling accurate detection of on-channel RF signals at weak power levels by synchronizing CD processing with training systems and applying automatic gain control, thus improving receiver performance and power management.
Implementation Method 1
The process of combining the received RF signal with a LO signal to produce an output signal is referred to as mixing, down-converting, up-converting, down-mixing, up-mixing or modulating the RF signal with the LO signal
Implementation Method 2
The ADC digitizes the signal from the analog processing block
Data Source
AI summary
A method of detecting an on-channel signal and synchronizing signal detection with correcting for DC offset errors in a direct conversion receiver is presented. A received signal is digitized, and a state machine operates to detect the presence of an on-channel signal. If the signal is not detected, a mixed mode training sequence is initiated in which the DC offset errors in both an analog and digital received signal path are corrected. While training, processing of the digitized samples by a digital signal processor and a host controller is suspended (while they are put into battery save mode) and the gain provided to subsequently received signals is minimized. The DC offset correction circuitry is bypassed and put into battery save mode at predetermined periods when DC offset correction is not performed.