Carrier-Based Memory Protection for Multiprocessor Systems
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Solution Overview
Problem
In multiprocessor systems, the performance penalty of requiring two physical memory references for virtual-to-physical address translation hampers memory protection, especially in large-scale distributed systems where protecting shared memory becomes difficult due to the tight coupling of translation look-aside buffers with processors.
Innovation Solution
Offloading memory protection to a communication carrier chip associated with the processor, which uses a carrier identification (ID) to determine whether the processor is permitted to access memory addresses, thereby decoupling memory protection from the processor and enabling scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If virtual memory management with paging is used for memory protection, then memory protection is achieved, but performance penalty increases due to requiring two physical memory references for address translation
Solution Approach 1:
The patent pre-loads translation information into the TLB before actual memory access occurs. The carrier identifies the processor and pre-establishes the mapping relationships, so when memory access is needed, the translation is already cached and ready, eliminating the need for two sequential memory references and improving access performance while maintaining protection.
Solution Approach 2:
The patent introduces a carrier as an intermediary component between the processor and memory. This carrier maintains translation look-aside buffers and performs address translation mediation, allowing the processor to access memory through the carrier which handles the translation caching, thus reducing the performance penalty of virtual memory management.
2Speed
If translation look-aside buffers are tightly coupled with processors for performance optimization, then memory access speed is improved, but memory protection scalability deteriorates in large-scale distributed systems
Solution Approach 1:
The patent segments the memory protection and address translation functionality from the processor core and places it in the carrier component. This segmentation allows each processor-carrier pair to have its own TLB for high-speed access, while the overall system can scale by adding more processor-carrier pairs without creating complex interdependencies, thus improving both speed and scalability.
Solution Approach 2:
The carrier acts as an intermediary that houses the TLB and translation logic separate from the processor. This intermediary structure enables independent optimization of translation speed while allowing the system to scale by adding more processor-carrier units, as each unit operates semi-independently with its own translation buffer.
3Reliability
If complex memory protection mechanisms are integrated within processors, then memory protection capability is enhanced, but device complexity increases
Solution Approach 1:
The patent extracts the complex memory protection and address translation mechanisms from the processor core and relocates them to the carrier component. This extraction simplifies the processor design by removing cumbersome protection logic, while the carrier assumes the responsibility for implementing sophisticated memory protection using carrier identification and translation buffering.
Solution Approach 2:
The carrier serves as an intermediary that handles complex memory protection tasks, allowing the processor to remain simple while still achieving robust protection. The carrier implements the sophisticated logic for carrier ID matching and address translation, shielding the processor from complexity while maintaining strong memory protection capabilities.
Data Source
AI summary
A method for memory protection in a multiprocessor system, involving receiving a request at a first carrier to perform a memory operation at a memory address, wherein the first carrier receives the request from a processor, determining by the first carrier whether the processor is permitted to access memory at the memory address using a carrier identification (ID) of a second carrier, wherein the second carrier is associated with a memory controller used to access the memory, and sending the request to the second carrier, if the processor is permitted to access the memory.