Carrier Structure With Notched Positioning Traces for Substrate Alignment

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Solution Overview

Problem

Conventional semiconductor packaging processes using lead frames are inadequate for high-integration and miniaturization requirements, as the small positioning holes on substrate strips can damage positioning pins and limit layout utilization.

Innovation Solution

A carrier structure with a main area for packaging substrates and a peripheral area featuring positioning holes and traces, where the traces are arranged to form notches, allowing for improved alignment and reduced damage to positioning pins while optimizing layout utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the size of the positioning hole is increased to facilitate positioning pin alignment, then the positioning pin damage is reduced, but the layout area of the positioning hole increases, causing the layout to exceed the removal portion and reducing the number of packaging substrates

Engineering Contradiction:
Improvepositioning pin damage preventionVSAvoidlayout utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The positioning structure is divided into two components: the positioning hole and the positioning trace. The positioning trace acts as a separate guiding element that segments the positioning function from the hole itself, allowing the hole to remain small while the trace provides the alignment guidance needed to prevent positioning pin damage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The positioning trace serves as an intermediary element between the positioning pin and the positioning hole. It provides a visible guide path that helps the positioning pin align correctly with the small positioning hole, preventing damage without requiring the hole to be enlarged.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the positioning hole size is kept small to maintain layout utilization, then more packaging substrates can be arranged, but the positioning pin is easily damaged by colliding with the substrate strip

Engineering Contradiction:
Improvelayout utilizationVSAvoidpositioning pin damage prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The positioning function is segmented into the small positioning hole (maintaining layout utilization) and the separate positioning trace (providing alignment guidance). This segmentation allows the hole to remain small for high layout utilization while the trace prevents positioning pin damage through guidance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The positioning trace acts as an intermediary guide that enables the positioning pin to accurately locate and enter the small positioning hole without colliding with the substrate strip, thus protecting the pin while maintaining compact layout.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the positioning trace surrounds the entire edge of the positioning hole, then alignment guidance is maximized, but the occupation area of the peripheral region increases

Engineering Contradiction:
Improvepositioning accuracyVSAvoidperipheral area occupation
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The positioning trace is designed with local quality by providing guidance only at critical sections where alignment is needed, rather than surrounding the entire positioning hole. This localized approach maintains positioning accuracy while minimizing the occupation area of the peripheral region.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of providing complete circumferential guidance (excessive action), the positioning trace applies partial guidance only where necessary for alignment. This partial action is sufficient to prevent positioning pin damage while reducing the area occupied in the peripheral region.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250126702A1Carrier structure
Publication Date: 2025.04.17 SILICONWARE PRECISION IND CO LTD
  • US20250126702A1 patent drawing
  • US20250126702A1 patent drawing
  • US20250126702A1 patent drawing

AI summary

A carrying structure is provided and is defined with a main area and a peripheral area adjacent to the main area, where a plurality of packaging substrates are disposed in the main area in an array manner, a plurality of positioning holes are disposed in the peripheral area, and a plurality of positioning traces are formed along a part of the edges of the plurality of positioning holes, such that the plurality of positioning traces are formed with notches. Therefore, a plurality of positioning pins on the machine can be easily aligned and inserted into the plurality of positioning holes by the design of the plurality of positioning traces.