Carrier Package with Chip and Component via Opening
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current packaging solutions for electronic chips face challenges in achieving high functionality, reliability, and cost-effectiveness, particularly in applications requiring high performance and reliability, such as micro-point-of-load applications, where traditional methods consume valuable space and limit performance.
Innovation Solution
A packaging architecture that involves mounting an electronic chip on a carrier, encapsulating it with a mold compound, and forming contact openings in the encapsulant to attach additional components, such as passive components, via these openings, ensuring electrical connectivity and positional accuracy while maintaining a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional packaging solutions are used for electronic chips, then manufacturing simplicity is maintained, but functionality is limited and space consumption increases
Solution Approach 1:
The patent merges multiple components (electronic chip, passive components, and their interconnections) into a single integrated package structure. The carrier substrate serves as a common platform for mounting both active and passive components, combining what would traditionally be separate packages into one unified structure, thereby reducing overall space consumption while enhancing functionality.
Solution Approach 2:
The patent implements a nested arrangement where passive components are positioned on the carrier substrate in close proximity to the electronic chip, with interconnection structures nesting through the substrate. This nested configuration allows components to be arranged in three-dimensional space efficiently, reducing the footprint while maintaining all necessary functional connections.
2Adaptability or versatility
If components are mounted on opposite sides of the carrier, then functionality and integration are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: first mounting the electronic chip on one side of the carrier substrate, then forming interconnection structures through the substrate, and finally mounting passive components on the opposite side. This segmentation of the manufacturing process makes the complex task of creating a high-integration package more manageable and systematic.
Solution Approach 2:
The carrier substrate acts as an intermediary element that facilitates connections between components on opposite sides. The substrate with its through-substrate interconnection structures serves as the mediating platform that enables integrated functionality while providing a standardized interface for mounting components, thereby reducing overall manufacturing complexity.
3Reliability
If contact openings are formed in the encapsulant, then electrical connectivity is improved, but manufacturing steps increase
Solution Approach 1:
The patent forms the interconnection structures through the carrier substrate during the initial packaging process, before the final encapsulation step. This preliminary formation of conductive paths ensures that electrical connectivity is established early in the manufacturing process, and the subsequent encapsulant formation simply protects these pre-established connections rather than creating them, thereby maintaining productivity while ensuring reliability.
Data Source
AI summary
A package comprising a carrier, at least one electronic chip mounted on one side of the carrier, an encapsulant at least partially encapsulating the at least one electronic chip and partially encapsulating the carrier, and at least one component attached to an opposing other side of the carrier via at least one contact opening.