Semiconductor Carrier Package Structure for Warpage Reduction
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Solution Overview
Problem
Conventional semiconductor packages face issues such as thermal stress mismatch leading to warping and cracking, adhesive layer peeling, void generation, and thermal damage due to high-temperature processes, along with complex and costly manufacturing processes.
Innovation Solution
An electronic package design featuring a carrier structure with grooves and through holes, where electronic elements are disposed in grooves and connected via conductive pillars, with a manufacturing method that forms circuit and conductive elements before placing elements, using laser to simplify processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the semiconductor chip is disposed in a previous process and undergoes high-temperature thermal processes, then the encapsulant and wiring structure can be formed, but the semiconductor chip accumulates thermal energy and may be damaged
Solution Approach 1:
The patent applies preliminary action by first forming the circuit structure and conductive pillars on the carrier before disposing the semiconductor chip. This allows subsequent high-temperature processes to be performed on the carrier without directly exposing the chip to cumulative thermal damage, as the chip is added later in the manufacturing sequence.
Solution Approach 2:
The patent segments the manufacturing process into distinct stages: first forming the carrier structure with circuit patterns and conductive pillars, then separately disposing the semiconductor chip, and finally forming the encapsulant. This segmentation allows optimization of each stage independently, reducing overall thermal burden on the chip.
2Ease of manufacture
If the coefficient of thermal expansion of the encapsulant and semiconductor chip mismatch, then the package can be assembled, but uneven thermal stress causes the encapsulant to warp and the chip to crack
Solution Approach 1:
The patent introduces a carrier structure as an intermediary between the encapsulant and semiconductor chip. The carrier serves as a mechanical support that absorbs and distributes thermal stress, preventing direct stress transmission to the chip and encapsulant interface, thereby reducing warping and cracking risks.
Solution Approach 2:
The patent changes the mechanical parameter structure by introducing a carrier with specific structural features (grooves, recessed portions) that modify the stress distribution characteristics. This structural modification allows the system to accommodate CTE mismatch without transmitting damaging stresses to the chip.
3Ease of manufacture
If the die-mounting adhesive layer is used to attach the semiconductor chip, then the chip can be mounted, but the adhesive layer peels and voids form during manufacturing
Solution Approach 1:
The patent extracts and eliminates the die-mounting adhesive layer from the structure. By directly disposing the semiconductor chip on the carrier structure without an intermediate adhesive layer, the source of peeling and void formation is removed, while chip mounting is still achieved through direct contact with the carrier's support structure.
4Ease of manufacture
If direct manufacturing of conductive pillars is performed, then the package can be assembled, but complicated processes such as exposure, development and electroplating increase manufacturing cost
Solution Approach 1:
The patent replaces the conventional multi-step electrochemical manufacturing process (exposure, development, electroplating) with a simplified mechanical or direct deposition method for forming conductive pillars. This substitution maintains the functional outcome while dramatically reducing process complexity and manufacturing cost.
Data Source
AI summary
An electronic package and a manufacturing method thereof are provided, wherein a circuit structure is formed on a carrier structure having a groove and through holes, a plurality of conductive pillars are disposed in a plurality of through holes to be electrically connected to the circuit structure, and electronic elements are placed in the groove to be electrically connected to the circuit structure, then a wiring structure is disposed on the carrier structure to be electrically connected to the plurality of conductive pillars, and wherein the carrier structure is a plate made of semiconductor material, thereby the manufacturing process can be simplified and the warpage problems can be reduced.