Power Electronics Carrier Pad Spacing for Delamination Control
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Solution Overview
Problem
The challenge in manufacturing power modules is the delamination of mold compound from metallized regions, leading to voids and increased production costs due to failed inspections, particularly in high-volume, cost-effective molding techniques.
Innovation Solution
A semiconductor package design with structured metallization layers on insulating substrates, where high-voltage difference nodes are spaced farther apart than low-voltage nodes, ensuring adequate electrical isolation and eliminating the need for adhesion promoter steps during molding, thus preventing delamination and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If molding techniques are used to manufacture power modules at high volumes, then productivity and manufacturing cost are improved, but delamination occurs between mold compound and metallized regions leading to reduced reliability
Solution Approach 1:
The patent applies different trench spacing configurations to different regions of the metallization layer based on voltage differences. High-voltage difference nodes have increased trench spacing to prevent delamination, while low-voltage difference nodes use standard spacing to maintain productivity. This localized differentiation resolves the contradiction by applying enhanced reliability measures only where electrically necessary.
Solution Approach 2:
The patent changes the physical parameter of trench spacing distance based on voltage difference requirements. By increasing the trench spacing parameter in high-voltage regions, the patent prevents delamination during molding while maintaining standard spacing in low-voltage regions to preserve manufacturing efficiency and productivity.
2Ease of manufacture
If standard trench spacing is used for all metal pads, then manufacturing simplicity is maintained, but high-voltage difference nodes are susceptible to delamination
Solution Approach 1:
The patent implements local quality by differentiating trench spacing based on the electrical characteristics of different pad regions. High-voltage difference nodes receive enhanced spacing for delamination prevention, while low-voltage nodes maintain standard spacing. This resolves the contradiction by making the structure adapt to local electrical requirements rather than applying uniform spacing.
Solution Approach 2:
The patent segments the metallization layer into regions based on voltage difference characteristics. By dividing the pads into high-voltage and low-voltage difference groups with different spacing requirements, the patent enables targeted design optimization that prevents delamination where needed while maintaining manufacturing simplicity elsewhere.
3Reliability
If increased trench spacing is applied to all pads, then delamination is prevented, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies enhanced trench spacing only to high-voltage difference nodes where delamination risk exists, rather than uniformly to all pads. This localized approach prevents delamination in critical regions while maintaining standard spacing in low-voltage regions, thereby avoiding unnecessary manufacturing complexity and cost increases.
Solution Approach 2:
The patent applies the delamination prevention measure (increased trench spacing) partially, only where electrically necessary for high-voltage difference nodes. This partial action approach provides sufficient reliability protection without the excessive complexity and cost that would result from applying the same measure to all pads uniformly.
4Reliability
If adhesion promoter steps are added during molding, then delamination is prevented, but manufacturing time and cost increase
Solution Approach 1:
The patent performs preliminary action by designing the trench spacing configuration before the molding process to inherently prevent delamination. By pre-configuring appropriate spacing in the metallization layer design, the patent eliminates the need for additional adhesion promoter steps during molding, thereby preventing delamination without adding manufacturing time or process complexity.
Solution Approach 2:
The patent replaces the chemical/adhesive approach (adhesion promoters) with a structural/electrical approach (optimized trench spacing). By designing the metallization geometry to prevent delamination through electrical field management rather than chemical adhesion, the patent eliminates the need for additional manufacturing steps while maintaining reliability.
Data Source
AI summary
A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance.