Carrier Aggregation RFIC Using One PLL for Multi-Carrier Mixing
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Solution Overview
Problem
Current RFIC designs require multiple phase-locked loops (PLLs) for carrier aggregation, leading to increased area occupation and high power consumption.
Innovation Solution
A radio-frequency integrated chip (RFIC) configured to use a single phase-locked loop (PLL) to support multiple carrier transmitters and receivers, with each carrier receiver or transmitter using frequency division to generate local oscillator signals for frequency translation, reducing the number of PLLs needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple PLLs are used for each carrier transmitter and receiver in carrier aggregation, then frequency stability and signal processing capability are improved, but chip area occupation and power consumption increase
Solution Approach 1:
The patent merges multiple PLL circuits into a single shared PLL that serves multiple carrier transmitters and receivers. The PLL generates a main frequency signal that is then divided by different division ratios to produce frequency signals for different carriers, reducing the total number of PLL circuits from multiple to one, thereby decreasing chip area while maintaining frequency stability across all carriers
Solution Approach 2:
The single PLL circuit is designed to perform multiple functions by generating a main frequency signal that can be divided into different frequency signals for different carriers. This universal frequency generation approach allows one PLL to replace multiple dedicated PLLs, achieving multi-functionality without sacrificing the frequency stability required for each individual carrier
2Reliability
If multiple PLLs are used for each carrier transmitter and receiver in carrier aggregation, then frequency stability and signal processing capability are improved, but power consumption increases
Solution Approach 1:
The patent merges multiple PLL circuits into a single shared PLL that serves multiple carrier transmitters and receivers. By consolidating the frequency generation function into one circuit, the total power consumption is reduced compared to running multiple separate PLLs, while still providing frequency stability for all carriers through the divided frequency signals
Solution Approach 2:
The single PLL circuit is designed to perform multiple functions by generating a main frequency signal that can be divided into different frequency signals for different carriers. This universal frequency generation approach allows one PLL to replace multiple dedicated PLLs, achieving multi-functionality while reducing power consumption
3Area of stationary object
If a single PLL is shared across multiple carrier transmitters and receivers, then chip area and power consumption are reduced, but frequency signal generation complexity increases
Solution Approach 1:
The patent segments the frequency signal generation process into two distinct stages: first, the PLL generates a main frequency signal; second, separate division circuits divide this main frequency into different frequency signals for different carriers. This segmentation simplifies the overall architecture by replacing multiple complex PLLs with one PLL plus simple division circuits, reducing chip area while managing complexity through functional decomposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the area and power consumption associated with multiple PLLs, while enabling efficient carrier aggregation by sharing a single PLL across multiple carrier receivers and transmitters.
Implementation Method 1
The PLL may be configured to output a first frequency signal having a first frequency to the first and second carrier receivers. The first analog mixer may translate the frequencies of the first carrier signal using a second frequency signal generated by dividing the first frequency signal, and the second analog mixer may translate the frequencies of the second carrier signal using a third frequency signal generated by dividing the first frequency signal.
Implementation Method 2
The first analog mixer is configured to translate frequencies of the first carrier signal in an analog domain. The second analog mixer is configured to translate frequencies of the second carrier signal in an analog domain.
Data Source
AI summary
Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for further translating the frequencies of the receive signal in the digital domain.