Carrier Structure Embedded with Semiconductor Chips

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Solution Overview

Problem

Conventional carrier structures for semiconductor chips face issues of warping due to insufficient rigidity and burr formation during cutting, whether made of organic resins or metals, leading to complex production processes and low yield.

Innovation Solution

A carrier structure comprising two metal plates with an adhesive material and etching stop layers, where semiconductor chips are embedded in cavities and secured by an adhesive layer, with etching grooves filled to prevent warping and burr formation, using a Cu metal layer for enhancement and circuit formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the carrier is made of organic resins, then the carrier can be easily manufactured, but the carrier becomes warped due to insufficient rigidity

Engineering Contradiction:
Improveease of manufactureVSAvoidwarping
Core Design Contradiction:
Ease of manufactureVSStability of the object's composition

Solution Approach 1:

The patent uses a composite structure consisting of a metal carrier plate combined with a resin layer. The metal plate provides the necessary rigidity to prevent warping, while the resin layer maintains ease of manufacture and provides adhesive functionality for mounting semiconductor chips. This composite approach resolves the contradiction by combining materials with complementary properties.

Inventive Principle:
Principle #40Composite materials

2Stability of the object's composition

If the carrier is made of metal, then the carrier has better strength for anti-warp, but metal burrs will be generated when cut by a cutting tool

Engineering Contradiction:
Improveanti-warp strengthVSAvoidburr formation
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

The patent performs preliminary etching to form grooves in the metal carrier plate before the final cutting process. These pre-formed grooves guide the cutting tool and reduce stress concentration, thereby minimizing burr formation during the subsequent cutting operation. This preliminary action resolves the contradiction by preparing the metal structure in advance to facilitate cleaner cutting.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If the build up circuit layer structure is asymmetric, then the carrier becomes warped under stress, but the asymmetric structure is required for functional reasons

Engineering Contradiction:
Improvefunctional asymmetryVSAvoidwarping
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent introduces a counterbalancing structure on the opposite side of the asymmetric build-up circuit layer. This counterweight structure compensates for the stress imbalance caused by the asymmetric functional elements, preventing the carrier from warping while preserving the necessary functional asymmetry. The counterweight acts as a mechanical balance to offset the warping tendency.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution prevents warping and burr formation, enhancing the carrier structure's rigidity and appearance, improving manufacturing reliability and yield by using metal plates with an adhesive material to secure semiconductor chips and fill etching grooves.

Implementation Method 1

an adhesive material is disposed between the two metal plates... secured by an adhesive layer... filled with the adhesive material

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS7768119B2Carrier structure embedded with semiconductor chip
Publication Date: 2010.08.03 PHOENIX PRECISION TECH CORP
  • US7768119B2 patent drawing
  • US7768119B2 patent drawing
  • US7768119B2 patent drawing

AI summary

A carrier structure embedded with semiconductor chips is disclosed, which comprises a core board and a plurality of semiconductor chips mounted therein. The core board comprises two metal plates between which an adhesive material is disposed. An etching stop layer is deposited on the both surfaces of the core board. Pluralities of cavities are formed to penetrate through the core board. The semiconductor chips each have an active surface on which a plurality of electrode pads are disposed, and those are embedded in the cavities and mounted in the core board. An etching groove formed on the core board between the neighboring semiconductor chips is filled with the adhesive material. The present invention avoids the production of metal burrs when the carrier structure is cut.