Carrier Substrate with Elevated Connection Pads for Bonding Reliability
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Solution Overview
Problem
Existing carrier substrates have connection pads and traces on the same horizontal plane, leading to oxidation issues and difficulty in accurately connecting components, as the solder mask layer exposes both, making it hard to distinguish between them.
Innovation Solution
A carrier substrate design featuring a dielectric layer with blind vias, an insulation layer with gradually increasing openings, and conductive blocks that elevate and expose connection pads, allowing for accurate component connection while preventing oxidation by covering traces with the insulation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If connection pads and traces are placed on the same horizontal plane with the solder mask layer exposing both, then the structure is simple and easy to manufacture, but the traces are exposed to oxidation and components cannot be accurately connected
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked structure by placing connection pads on different horizontal planes. The first connection pads are located on a first horizontal plane while the second connection pads are on a second horizontal plane, creating vertical separation that allows the solder mask layer to selectively expose only the first connection pads without exposing traces, thereby preventing oxidation and improving bonding reliability.
Solution Approach 2:
The patent segments the connection pads into two distinct groups located on different horizontal planes. The first connection pads are positioned on the first horizontal plane and are exposed by the solder mask layer, while the second connection pads are positioned on the second horizontal plane and remain covered. This segmentation allows differentiated treatment of each pad type, enabling accurate component connection to the exposed first connection pads while protecting traces from oxidation.
2Device complexity
If the solder mask layer exposes both connection pads and traces, then the structure is simple, but it is difficult to distinguish connection pads from traces for accurate component connection
Solution Approach 1:
The patent uses vertical dimensionality to separate connection pads from traces in the horizontal plane. By positioning first connection pads on the first horizontal plane and second connection pads on the second horizontal plane, the solder mask layer can be designed to expose only the first connection pads while covering the traces on the first horizontal plane. This spatial separation in the vertical dimension makes it easy to distinguish connection pads from traces during component assembly.
Solution Approach 2:
The patent applies different exposure characteristics to different regions of the solder mask layer. The first connection pads are located in regions where the solder mask layer is removed to expose the pads, while the traces on the first horizontal plane remain covered by the solder mask layer. This local differentiation in quality (exposed vs. covered) enables clear distinction between connection pads and traces, facilitating accurate component connection.
3Device complexity
If traces are exposed from the outside of the solder mask layer, then the structure is simple, but oxidation phenomenon occurs affecting electrical performance
Solution Approach 1:
The solder mask layer serves as an intermediary protective barrier between the traces and the external environment. By designing the solder mask layer to cover the traces on the first horizontal plane while exposing only the first connection pads, the traces are protected from oxidation by the solder mask layer, thereby maintaining electrical performance without requiring complex additional protective structures.
Solution Approach 2:
The patent converts the potential harm of trace exposure to oxidation into a benefit by using the solder mask layer's exposure pattern to selectively protect traces while exposing connection pads. The same solder mask layer that could potentially expose traces to oxidation is instead designed to cover traces and expose only the connection pads, turning the exposure issue into a beneficial selective exposure that prevents oxidation while enabling component connection.
Data Source
AI summary
A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings exposing the first circuit layer. The conductive blocks fill the first openings and connect with the first circuit layer. A top surface of each of the conductive blocks is higher than the third surface of the insulation layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.