Carrier Substrate Junctions for ESD Protection in IC Backside Processing
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Solution Overview
Problem
Integrated circuits face challenges in scaling down due to plasma-induced electrostatic discharge (ESD) damage during backside processing, as floating interconnect features lack a discharge path, leading to potential degradation or destruction of semiconductor devices.
Innovation Solution
A carrier substrate with integrated junctions is bonded to the integrated circuit, providing a conductive path to ground for plasma-induced charges through doped regions and conductive vias, thereby reducing the risk of ESD damage during backside processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If backside processing is performed on integrated circuits, then further scaling of memory and logic cells is enabled, but plasma-induced electrostatic discharge damage occurs to floating interconnect features
Solution Approach 1:
A carrier substrate with doped junction regions is introduced as an intermediary between the floating interconnect features and ground. The carrier substrate includes doped regions that form diode structures, acting as a mediator to safely channel plasma-induced charges to ground, thereby protecting the interconnect features from ESD damage while enabling continued backside processing operations
Solution Approach 2:
The carrier substrate with protective doped junctions is bonded to the interconnect region before backside processing begins. This preliminary action establishes the charge dissipation path in advance, ensuring that when plasma processing occurs, the floating interconnect features are already protected from ESD damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces plasma-induced ESD damage, allowing for further scaling of memory and logic cells by grounding floating interconnect features, thus protecting the semiconductor devices and enabling continued backside processing without performance degradation.
Implementation Method 1
protecting an integrated circuit from damage caused by plasma-induced electrostatic discharge (ESD)
Implementation Method 2
providing a conductive path to ground for plasma-induced charges
Implementation Method 3
plasma-induced electrostatic discharge (ESD) damage during backside processing
Data Source
AI summary
Techniques are provided for protecting integrated circuits from plasma-induced electrostatic discharge (ESD) using a carrier substrate with integrated junctions. According to some embodiments, the various metal features within an interconnect region above a plurality of semiconductor devices are electrically coupled to one or more conductive pads on a bonded carrier substrate. The conductive pads provide a contact to underlying doped regions within the carrier substrate that form one or more PN junctions. This provides the ability to electrically ground metal features in the interconnect region via the carrier substrate. Formation of additional interconnect layers such as those provided during far back end of line (FBEOL) processing, can proceed while causing less plasma-induced ESD damage to the integrated circuit, because the interconnect region is connected to ground of carrier substrate by way of PN junctions, thus providing a discharge path for charge that develops during subsequent processing.