Carrier Substrate For Semiconductor Transfer Printing
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Solution Overview
Problem
The existing methods for manufacturing semiconductor components on a carrier substrate for transfer printing to a receiving substrate are complex and require numerous process steps, leading to increased effort and mechanical stresses due to lattice constant differences between materials like silicon and gallium nitride.
Innovation Solution
The method involves providing a carrier substrate with a selected crystal orientation and dielectric regions for selective epitaxial growth, which reduces mechanical stresses and simplifies the process by defining the semiconductor structure's size and shape, allowing for reduced etching and masking steps, and enabling efficient transfer printing without additional lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transfer printing methods are used with multiple release layers and etching steps, then semiconductor components can be transferred from one substrate to another, but the process complexity and number of manufacturing steps increase significantly
Solution Approach 1:
The invention extracts and eliminates the complex multi-layer release structure from the transfer printing process. Instead of using multiple release layers with sequential etching steps, the patent employs a single etchable release layer that can be removed in one step, significantly simplifying the manufacturing process while maintaining the essential transfer printing functionality
Solution Approach 2:
The single etchable release layer performs multiple functions that were previously distributed across multiple layers: it enables component release, defines the release pattern, and facilitates stamp adhesion. This multi-functional layer reduces process complexity while achieving the same transfer printing objectives
2Stability of the object's composition
If selective epitaxial growth is used to reduce mechanical stresses from lattice constant differences, then stress is minimized, but the requirement for precise crystal orientation and dielectric regions increases process complexity
Solution Approach 1:
The invention performs preliminary actions by pre-defining dielectric regions and selecting appropriate crystal orientations before the epitaxial growth process. This preliminary preparation ensures that when selective epitaxial growth occurs, mechanical stresses are automatically minimized without requiring complex real-time adjustments during manufacturing
Solution Approach 2:
The patent applies local quality by creating dielectric regions at specific locations where epitaxial growth should occur. These localized dielectric structures guide the epitaxial process to grow semiconductor material only in desired areas with proper crystal orientation, reducing mechanical stress at critical interfaces while maintaining simplicity in the overall process
3Manufacturing precision
If dielectric regions are used to define active regions for selective epitaxial growth, then the size and shape of semiconductor structures are precisely controlled, but additional masking and etching steps are required
Solution Approach 1:
The dielectric regions serve as intermediary structures that simplify the patterning process. Instead of using complex photomask sequences to define active regions, the dielectric regions act as physical intermediaries that automatically define where epitaxial growth should occur, eliminating the need for multiple masking and etching steps while maintaining precise structural control
4Ease of operation
If connection elements are fractured to release components from the donor substrate, then transfer printing is enabled, but mechanical stresses and potential damage to components increase
Solution Approach 1:
The invention applies beforehand cushioning by designing the connection elements and release process to minimize mechanical stress. The single etchable release layer is engineered to fracture in a controlled manner that releases components gently, and the stamp material is selected to provide cushioning during the release process, preventing damage to sensitive semiconductor structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the complexity and effort in manufacturing semiconductor structures, minimizing mechanical stresses and allowing for high-efficiency transfer of components like transistors with high electron mobility to a receiving substrate, such as CMOS environments, while maintaining compatibility with further processing.
Implementation Method 1
producing a semiconductor structure to be transferred by depositing at least one semiconductor layer on the active region by selective epitaxial growth
Implementation Method 2
etching is performed for removing semiconductor material beneath the semiconductor structure
Data Source
AI summary
A carrier substrate for semiconductor structures which can be transferred by transfer printing, and manufacture of the semiconductor structures on the carrier substrate. The number of the required process steps and thus the required effort is to be generally reduced in the manufacture of component structures on a carrier substrate for providing the component structures in a state in which they can be transferred to a further substrate by transfer printing. For this purpose, it is suggested to produce semiconductor structures to be transferred on a carrier substrate. The method comprises providing a carrier substrate (10) including a semiconductor material with a selected crystal orientation. An active region (11) is produced which has an exposed semiconductor surface (11) and is almost completely delimited by dielectric regions (30, 80) including an isolating dielectric material. Forming a semiconductor structure (40) to be transferred by depositing at least one semiconductor layer on the active region (11) is provided. Removal of at least a part or portion of the dielectric material is performed as well as an etching and removal of semiconductor material beneath the semiconductor structure (40).