Carrier Substrate for 3D Metal Interconnect Assembly
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Solution Overview
Problem
Current three-dimensional metal interconnect technologies face limitations in integrating disparate semiconductor die with different technologies and sizes, leading to wasted space, cumulative defect densities, and limited configurational flexibility, as well as requiring precise and costly pick-and-place processes.
Innovation Solution
A self-assembly process using a carrier substrate with cavities of specific shapes and sizes to align and bond die from different technologies, allowing for fluidic self-assembly or pick-and-place alignment, followed by wafer bonding to form high-density metal interconnects, enabling the integration of die with varying sizes and technologies while reducing defect densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wafer bonding technique is used to bond two wafers with different die technologies, then high density interconnects can be achieved, but the die must have the same size, spacing, and repetition rate which limits configurational flexibility
Solution Approach 1:
The patent segments the bonding process into two independent stages: first bonding the first wafer to a carrier wafer, then bonding the second wafer to the carrier wafer. This segmentation allows each wafer to be bonded independently to the same carrier, enabling different die sizes, spacings, and repetition rates on each wafer while still achieving high interconnect density through the carrier-mediated bonding process
Solution Approach 2:
The carrier wafer serves as an intermediary element that mediates between the first wafer and second wafer. Each wafer is bonded to the carrier wafer separately, allowing the carrier to accommodate different geometries and configurations for each wafer type while maintaining high-density interconnect formation through the bonding interfaces
2Reliability
If pick and place process is used to assemble individual die, then known good die can be selected, but the process is precise and costly
Solution Approach 1:
The patent merges multiple individual die onto a single carrier wafer in a batch process before final assembly. By combining multiple die selection and bonding operations into a single batch process, the method achieves the reliability of selecting known good die while eliminating the need for repeated precise pick-and-place operations, thereby reducing assembly cost and complexity
Solution Approach 2:
The patent performs preliminary bonding of multiple die to the carrier wafer before final assembly. This preliminary action allows for batch testing and selection of known good die, and the pre-assembled carrier structure can then be handled as a single unit, reducing the precision and cost requirements of the final pick-and-place operation
3Adaptability or versatility
If stacked die technique is used to join disparate chips, then integration of different technologies is achieved, but wasted space occurs due to size matching requirements
Solution Approach 1:
The patent segments the stacking process by introducing a carrier wafer as an intermediate platform. Different sized die can be selectively placed on the carrier wafer in specific arrangements that optimize space utilization, and the carrier provides a common bonding interface that accommodates various die geometries without requiring size matching between stacked die
Solution Approach 2:
The patent applies local quality by allowing different die to be positioned at different locations on the carrier wafer according to their specific size and configuration requirements. Each die can be optimally positioned to minimize wasted space while maintaining the necessary bonding interfaces, rather than requiring all die to conform to a uniform size pattern
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient, high-density interconnects between die of different technologies, reducing parasitic characteristics and defect densities, and enabling the integration of diverse semiconductor die without the need for precise pick-and-place alignment, thus improving the efficiency and cost-effectiveness of semiconductor assembly.
Implementation Method 1
wafer bonding to form high-density metal interconnects
Data Source
AI summary
An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks.