Carrier Wafer Integration for Low-Loss 3D Stacked Semiconductors
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Solution Overview
Problem
Conventional surface-mounting of passive devices in semiconductor devices leads to significant parasitic losses due to large electrical distances, causing latency in power supply to stacked semiconductor devices in complex 3D architectures.
Innovation Solution
Integrating passive devices, such as capacitors and inductors, into a carrier wafer with through-silicon vias, which reduces the interconnect distance between passive components and semiconductor dies, using hybrid bonding and grinding techniques to expose conductive portions of the vias for improved power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If passive devices are surface-mounted in conventional semiconductor devices, then device complexity is reduced and ease of manufacture is improved, but interconnect distance increases causing parasitic losses and power supply latency
Solution Approach 1:
The patent merges passive devices with the carrier wafer by forming them within the carrier wafer substrate itself, rather than surface-mounting them separately. This integration reduces interconnect distance and parasitic losses while the carrier wafer serves as both the passive device substrate and the mounting platform for active devices, combining multiple functions into a single structure.
Solution Approach 2:
The patent transitions from two-dimensional surface mounting to three-dimensional integration by forming passive devices within the vertical depth of the carrier wafer. Through-silicon vias extend vertically to connect passive devices to active devices on the surface, utilizing the third dimension to reduce interconnect path length and parasitic effects.
2Ease of manufacture
If passive devices are surface-mounted, then ease of manufacture is improved, but interconnect distance increases causing voltage drops and power supply latency
Solution Approach 1:
The carrier wafer is formed to integrate both active and passive devices within a single substrate, eliminating the need for separate surface-mounting processes. Passive devices are fabricated directly in the carrier wafer using standard semiconductor manufacturing techniques, maintaining ease of manufacture while dramatically reducing interconnect distance through vertical via connections.
Solution Approach 2:
The patent utilizes vertical through-silicon vias to connect passive devices within the carrier wafer to active devices on the surface, transitioning from horizontal interconnect paths to vertical ones. This dimensional change reduces the effective interconnect length while maintaining compatibility with standard manufacturing processes.
3Reliability
If through-silicon vias are formed to reduce interconnect distance, then power delivery performance is improved, but manufacturing complexity increases
Solution Approach 1:
Through-silicon vias are formed in the carrier wafer during the wafer fabrication process before active devices are mounted. This preliminary formation of interconnect structures allows subsequent mounting and wiring steps to proceed without additional via drilling or complex alignment procedures, reducing overall manufacturing complexity despite the added via structures.
Solution Approach 2:
The carrier wafer acts as an intermediary structure that pre-integrates passive devices and forms through-silicon vias to facilitate direct vertical connections to active devices. This intermediary carrier wafer absorbs the manufacturing complexity of via formation while providing simplified interfaces for subsequent assembly steps.
Data Source
AI summary
A method of forming a semiconductor assembly includes forming a set of through-silicon vias in a carrier wafer, where a layer of the carrier wafer includes integrated devices. A die is coupled to a top surface of the carrier wafer including the set of through-silicon vias using hybrid bonding. One or more connection layers of the die are coupled to one or more of the through-silicon vias and coupled to one or more of the integrated devices. A second wafer is coupled to a top surface of the die. An amount is removed from a bottom surface of the carrier wafer that is parallel to and opposite to the top surface of the carrier wafer to reveal a conductive portion of at least one of the through-silicon vias.