Carrier-Wafer ESD Protection for Backside Power Rail Integration
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Solution Overview
Problem
Existing semiconductor manufacturing technologies ineffectively utilize the real estate on device wafers, as carrier wafers are primarily used for mechanical support, leaving limited space for forming active devices that require higher operating speeds and process nodes, while failing to adequately protect against electrostatic discharge (ESD) which can cause performance degradation or failure.
Innovation Solution
The semiconductor device incorporates an ESD protection circuit formed on a carrier wafer, operatively coupled to power rails on the back side of the device wafer, allowing for more efficient use of the device wafer's real estate and improved overall performance by dissipating ESD current transients, thereby preventing thermal damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If carrier wafers are used only for mechanical support, then structural stability is maintained, but device wafer real estate utilization is insufficient
Solution Approach 1:
The carrier wafer is transformed from a single-function mechanical support structure into a multi-functional platform that simultaneously provides structural support and hosts ESD protection circuits. The ESD circuit is formed directly on the carrier wafer, allowing it to serve both as a mechanical carrier and as an active protection circuit substrate, thereby resolving the contradiction between maximizing device wafer real estate and ensuring ESD protection reliability.
Solution Approach 2:
The ESD protection circuit is implemented on the carrier wafer in a different spatial dimension than the primary active devices on the device wafer. This dimensional separation allows the device wafer to be fully utilized for high-performance devices while the carrier wafer provides ESD protection functionality, effectively resolving the real estate utilization issue without compromising protection reliability.
2Reliability
If ESD protection circuit is added to protect against electrostatic discharge, then reliability is improved, but device wafer real estate is reduced
Solution Approach 1:
The semiconductor manufacturing system is segmented into two distinct functional substrates: the device wafer for active devices and the carrier wafer for ESD protection circuits. This segmentation allows each substrate to be optimized for its specific function, with the device wafer dedicated to high-performance devices and the carrier wafer dedicated to ESD protection, thereby resolving the contradiction between reliability improvement and real estate utilization.
Solution Approach 2:
The carrier wafer acts as an intermediary substrate that hosts the ESD protection circuit and interfaces with the device wafer. By placing the ESD circuit on the carrier wafer rather than directly on the device wafer, the invention mediates between the need for ESD protection and the need to maximize device wafer real estate, allowing both requirements to be satisfied simultaneously.
3Reliability
If more space is allocated for ESD protection, then reliability is improved, but productivity of high-speed devices is reduced
Solution Approach 1:
The fabrication process is segmented into separate workflow streams: one for device wafer processing and another for carrier wafer ESD circuit formation. This segmentation allows parallel processing and eliminates the need to allocate device wafer space for ESD circuits, thereby maintaining high productivity for high-speed devices while ensuring comprehensive ESD protection through the carrier wafer implementation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of semiconductor devices by effectively utilizing the device wafer's real estate for higher-speed and smaller-process-node devices while providing robust ESD protection, improving the reliability and operational integrity of integrated circuits.
Implementation Method 1
an ESD protection circuit formed on a carrier wafer, operatively coupled to power rails on the back side of the device wafer
Data Source
AI summary
A semiconductor device includes a device wafer having a first side and a second side. The first and second sides are opposite to each other. The semiconductor device includes a plurality of first interconnect structures disposed on the first side of the device wafer. The semiconductor device includes a plurality of second interconnect structures disposed on the second side of the device wafer. The plurality of second interconnect structures comprise a first power rail and a second power rail. The semiconductor device includes a carrier wafer disposed over the plurality of first interconnect structures. The semiconductor device includes an electrostatic discharge (ESD) protection circuit formed over a side of the carrier wafer. The ESD protection circuit is operatively coupled to the first and second power rails.