Carrier-Wafer BEOL ESD Array for Low-Area IC Protection
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Solution Overview
Problem
Integrated circuits (ICs) face challenges in efficiently protecting against electrostatic discharge (ESD) events due to the large on-chip area consumption and limited semiconductor fabrication technology, which can lead to damage from overvoltage and high power dissipation, especially in deep sub-micron processes.
Innovation Solution
A semiconductor structure with an ESD protection network is implemented using a carrier wafer with patterned ESD protection circuits, including diodes and power clamp circuits, that divert ESD pulses and reduce on-chip layout area by fabricating these circuits on the carrier wafer, allowing for efficient routing of ESD signals and minimizing parasitic discharge effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection networks are implemented using conventional semiconductor fabrication technology, then ESD protection functionality is achieved, but on-chip area consumption increases significantly
Solution Approach 1:
The patent implements ESD protection circuits in the BEOL layers (metal interconnect layers) rather than in the active device layer, effectively moving the protection functionality to a different dimensional plane. This allows the ESD protection network to share the same physical chip area without consuming additional active device area, as the protection circuits are formed using existing metal routing layers above the active devices.
Solution Approach 2:
The patent utilizes existing BEOL metal interconnect layers and routing structures for dual purposes: both for normal circuit interconnection and for ESD protection current diversion. By making the existing metal infrastructure serve multiple functions, no additional dedicated area is required for ESD protection, as the same metal layers handle both signal routing and ESD current dissipation.
2Reliability
If ESD protection networks are designed to handle high power dissipation, then ESD event protection is improved, but device complexity increases
Solution Approach 1:
The patent leverages the inherent properties of the BEOL metal interconnect structure to naturally handle ESD current dissipation. The existing metal layers, vias, and contact structures are utilized as the ESD protection pathway, eliminating the need for separately designed complex ESD protection circuits. The infrastructure serves itself for both normal operation and ESD protection.
Solution Approach 2:
The patent combines the ESD protection function with the existing metal interconnect infrastructure, merging two separate functions (signal routing and ESD protection) into a unified structure. This integration eliminates the need for separate ESD protection circuit design, thereby reducing overall device complexity while maintaining robust ESD protection capability.
3Productivity
If semiconductor fabrication technology is scaled down to deep sub-micron processes, then IC integration density is improved, but vulnerability to ESD stress increases
Solution Approach 1:
By implementing ESD protection in the BEOL layers rather than in the active device layer, the patent protects the vulnerable deep sub-micron devices without requiring changes to the already-optimized active device design. The protection mechanism operates in a different dimensional plane (metal interconnect layer), allowing high integration density in the active devices while providing robust ESD protection through the metal routing network.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively protects ICs from ESD events while reducing on-chip area usage, increasing routing resources, and preventing damage by diverting ESD pulses and managing high currents, thus enhancing IC reliability and functionality.
Implementation Method 1
electrostatic discharge (ESD) events arising from the abrupt release of charge from an object or person to an IC chip
Data Source
AI summary
An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.