Carrier-Wafer ESD Circuit Layout for Device Wafer Space
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Solution Overview
Problem
Existing semiconductor manufacturing technologies ineffectively utilize the real estate on device wafers, as carrier wafers are primarily used for mechanical support, leaving limited space for forming active devices that require higher operating speeds and smaller process nodes, while failing to adequately protect against electrostatic discharge (ESD) which can cause performance degradation or failure.
Innovation Solution
The semiconductor device incorporates an ESD protection circuit formed on a carrier wafer, which is operatively coupled to power rails on the back side of the device wafer, allowing more space on the device wafer for forming active devices and improving overall performance by dissipating ESD current transiently through a discharging channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If carrier wafers are used primarily for mechanical support, then structural stability is maintained, but device wafer real estate utilization is insufficient
Solution Approach 1:
The carrier wafer is transformed from a single-function mechanical support structure into a multi-functional platform that simultaneously provides structural support and hosts ESD protection circuits. The ESD circuit is formed directly on the carrier wafer using the same semiconductor fabrication processes, enabling the carrier to serve dual purposes: maintaining wafer stability during manufacturing and providing electrostatic discharge protection for the device.
2Reliability
If more space is allocated on device wafer for ESD protection circuits, then ESD reliability is improved, but space for active devices with higher operating speeds is reduced
Solution Approach 1:
The patent separates the ESD protection function from the active device function by placing them on different wafers. The ESD circuit is formed on the carrier wafer while active devices are formed on the device wafer, allowing each to be optimized independently without competing for space. This spatial segmentation resolves the trade-off between ESD protection capability and active device performance.
3Device complexity
If ESD protection circuits are integrated on the same wafer as active devices, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent moves the ESD circuit from the two-dimensional plane of the device wafer to a separate carrier wafer dimension. This dimensional separation allows ESD circuits to be fabricated independently at their optimal process nodes without constraining the active devices on the device wafer. The wafers are then bonded together, achieving integration without compromising manufacturing precision for either circuit type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively protects semiconductor devices from ESD, enhances the utilization of device wafer real estate, and improves overall performance by allowing more space for forming devices with higher operating speeds and smaller process nodes on the device wafer.
Implementation Method 1
ESD can cause a short sudden surge of electric charge within the integrated circuit, which can ultimately cause an integrated circuit to fail
Data Source
AI summary
A semiconductor device includes a device wafer including a first side and a second side opposite to each other, and a carrier wafer disposed over the first side of the device wafer. The carrier wafer includes an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first diode and a second diode. The first diode is operatively coupled to a first power rail, and the second diode is operatively coupled to a second power rail at least through the device wafer.