Wafer-Level Chip Scale Package Carrier Wafer Handling
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Solution Overview
Problem
The handling of fragile piezoelectric substrates in MEMS devices is challenging due to their fragility, which complicates the fabrication of chip-scale packages, especially for components like SAW or BAW filters.
Innovation Solution
A wafer-level chip-scale package design that includes a polymeric body with a conductive via and a piezoelectric substrate bonded using transient liquid phase or solder bonds, along with a seal ring and dielectric layers to create a hermetically sealed cavity, allowing for the integration of interdigital electrodes and passive devices like inductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If piezoelectric substrates are used for MEMS devices, then device performance is improved, but handling difficulty increases due to substrate fragility
Solution Approach 1:
The patent performs preliminary actions by forming the piezoelectric substrate and MEMS devices on a carrier wafer before substrate release. The carrier wafer provides mechanical support during fabrication, and release holes are pre-formed to enable controlled substrate release. This preliminary structuring allows fragile substrates to be handled indirectly through the robust carrier wafer, resolving the contradiction between device performance and handling difficulty.
Solution Approach 2:
The carrier wafer acts as an intermediary between the fragile piezoelectric substrate and the external handling environment. The substrate is bonded to the carrier wafer during fabrication, allowing the strong carrier to protect and transport the fragile substrate. Release holes provide controlled access points for substrate release without requiring direct handling of the fragile substrate itself, thus resolving the handling difficulty while maintaining device performance.
2Productivity
If wafer-level chip-scale packaging is used, then manufacturing efficiency is improved, but hermetic sealing difficulty increases
Solution Approach 1:
The patent performs preliminary sealing actions by forming seal structures (such as seal rings or sealed cavities) in the carrier wafer before substrate release. These seal structures are pre-configured to create hermetic barriers that will enclose the MEMS devices after substrate release. This preliminary sealing approach maintains the high manufacturing efficiency of wafer-level processing while achieving reliable hermetic sealing, as the sealing structures are formed in bulk before device release.
Solution Approach 2:
The patent segments the carrier wafer by forming release holes that define sealed cavities. The carrier wafer is divided into multiple sealed regions, each containing MEMS devices, while maintaining overall wafer-level processing efficiency. This segmentation allows hermetic sealing to be achieved at the cavity level while preserving the productivity benefits of wafer-level manufacturing through parallel processing of multiple devices.
3Device complexity
If fragile substrates are handled directly, then fabrication simplicity is maintained, but substrate damage risk increases
Solution Approach 1:
The carrier wafer serves as an intermediary that eliminates direct handling of fragile substrates throughout the fabrication process. All processing, bonding, and assembly operations are performed on the robust carrier wafer, which protects the fragile substrate from mechanical damage. The substrate remains bonded to the carrier until the final release stage, at which point pre-formed release holes enable controlled substrate detachment without requiring direct substrate handling, thus maintaining fabrication simplicity while dramatically reducing damage risk.
Solution Approach 2:
The carrier wafer provides beforehand cushioning and mechanical support to the fragile piezoelectric substrate during all fabrication operations. This protective support structure absorbs mechanical stresses and prevents substrate damage that would occur with direct handling. The carrier wafer acts as a cushioning layer that protects the substrate until the final release, at which point controlled etching through pre-formed release holes enables safe substrate detachment without direct mechanical contact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the handling and integration of fragile piezoelectric substrates, providing a robust and hermetically sealed environment for MEMS devices, improving the reliability and performance of chip-scale packages in electronic devices such as RF modules.
Implementation Method 1
The piezoelectric substrate may be directly bonded to the upper end of the conductive via with one of a transient liquid phase bond and a solder bond.
Implementation Method 2
The piezoelectric substrate may be directly bonded to the upper end of the conductive via with one of a transient liquid phase bond and a solder bond.
Implementation Method 3
The seal ring may surround the cavity and hermetically seal the cavity.
Implementation Method 4
a dielectric layer disposed on walls of the cavity and hermetically sealing the cavity
Data Source
AI summary
A wafer-level chip-scale package includes a polymeric body having a conductive via passing through the polymeric body and a piezoelectric substrate directly bonded to an upper end of the conductive via. The wafer-level chip-scale package further includes a cavity defined between a portion of the polymeric body and the piezoelectric substrate and a metal seal ring disposed in the body and having an upper end bonded to the piezoelectric substrate, the metal seal ring passing only partially through the body.