Carrier Wafer Sacrificial Layer for Semiconductor Thinning
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Solution Overview
Problem
The high cost and limited reusability of carrier wafers due to the need for frequent replacement during the thinning and planarization process of semiconductor devices, as the carrier wafers lose structural rigidity after thinning, result in significant expenses in modern semiconductor fabrication.
Innovation Solution
A sacrificial material is applied to the carrier wafer, which is partially removed to planarize and support the device wafer during thinning, allowing for reuse of the carrier wafer by maintaining planarity and structural integrity, and enabling cost-effective and precise thinning and planarization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the carrier wafer is thinned during planarization to match the device wafer thickness, then the planarity of the device wafer is improved, but the structural rigidity of the carrier wafer deteriorates, limiting its reusability
Solution Approach 1:
The solution divides the carrier system into two independent parts: a reusable carrier wafer and a consumable sacrificial layer. The sacrificial layer is applied to the carrier wafer surface and thinned along with the device wafer, while the carrier wafer itself remains thick and structurally sound for repeated use.
Solution Approach 2:
The sacrificial layer is designed as a disposable, low-cost material that is consumed during the planarization process. This layer is thinned and removed after use, allowing the expensive carrier wafer to be preserved and reused multiple times while achieving the necessary planarity.
2Manufacturing precision
If the carrier wafer is thinned to enable planarization, then the planarity reference function is improved, but the carrier wafer must be replaced frequently, increasing costs
Solution Approach 1:
The system is segmented into a permanent carrier wafer and a temporary sacrificial layer. The sacrificial layer provides the planarity reference function during processing and is then discarded, while the carrier wafer retains its structural integrity for reuse.
Solution Approach 2:
The sacrificial layer is applied to the carrier wafer before bonding the device wafer. This preliminary action creates the necessary planarity reference surface that will be thinned during processing, protecting the carrier wafer from direct thinning operations.
3Device complexity
If conventional carrier wafers are used without sacrificial material, then the process is simpler, but the carrier wafer loses rigidity and must be discarded after limited use
Solution Approach 1:
The sacrificial layer acts as an intermediary between the carrier wafer and the thinning/planarization process. It absorbs the mechanical stress and material removal, protecting the carrier wafer from losing structural integrity while enabling the necessary processing.
Solution Approach 2:
A low-cost sacrificial material is introduced that is consumed during processing. This disposable layer protects the expensive carrier wafer, making the overall process more economical despite the added material step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the planarity and reduces the cost of the thinning process, allowing for more efficient and consistent semiconductor device processing, increasing yield and reducing variations in device wafer thickness, while enabling the reuse of carrier wafers, thereby lowering overall expenses.
Implementation Method 1
planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness
Implementation Method 2
adhering a surface of the device wafer to an opposing surface of the carrier wafer with a bonding material
Data Source
AI summary
A method of processing a device wafer comprising applying a sacrificial material to a surface of a carrier wafer, adhering a surface of the device wafer to an opposing surface of the carrier wafer, planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness thereof, and planarizing an opposing surface of the device wafer. A wafer assembly is also disclosed.