Carrier Wafer Stress Patterning for 3D Chip Alignment
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Solution Overview
Problem
The challenge in manufacturing 3D-stacked semiconductor devices lies in the horizontal distortion of semiconductor chips during bonding, leading to misalignment, disconnection, and warpage issues due to bent or warped BEOL layers, which affects the performance of the stacked devices.
Innovation Solution
Incorporating patterns with stress materials on carrier wafers that expand or shrink thermally to control the bending or warpage of semiconductor chip bonding surfaces, ensuring flat and conformal bonding of BEOL or BSPDN layers during the thermal bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If semiconductor chips are bonded through thermal process, then bonding strength is improved, but horizontal distortion and warpage occur
Solution Approach 1:
The patent applies preliminary anti-action by forming patterns with stress materials on the carrier wafer before thermal bonding. These patterns generate pre-stress that counteracts the horizontal distortion and warpage that would otherwise occur during thermal bonding, allowing the BEOL layer to remain substantially flat throughout the bonding process
Solution Approach 2:
The patent utilizes parameter changes by controlling the thermal expansion coefficients of different materials in the carrier wafer patterns. By selecting materials with appropriate thermal expansion properties and controlling the thermal bonding parameters, the patent achieves flat bonding surfaces while maintaining strong bonding through the thermal process
2Adaptability or versatility
If BEOL layer is bent or warped, then manufacturing process flexibility is improved, but alignment precision deteriorates
Solution Approach 1:
The patent prevents alignment precision deterioration by applying preliminary anti-action through stress material patterns that keep the BEOL layer substantially flat before bonding. This pre-compression or pre-tension counteracts any bending forces, ensuring that metal lines and vias remain properly aligned and connected across the bonding interface
Solution Approach 2:
The patent applies local quality by creating localized patterns with stress materials at specific regions of the carrier wafer. These patterns are strategically positioned to provide localized stress compensation where needed, maintaining flatness and alignment precision in critical bonding areas while allowing process flexibility elsewhere
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses misalignment and warpage issues, enhancing the performance and reliability of 3D-stacked semiconductor devices by ensuring precise and stable bonding surfaces.
Implementation Method 1
patterns with stress materials on carrier wafers that expand or shrink thermally to control the bending or warpage of semiconductor chip bonding surfaces
Data Source
AI summary
Provided is a semiconductor device that includes: a 1st carrier wafer; and a 1st semiconductor chip on the 1st carrier wafer, wherein the 1st carrier wafer includes at least one 1st pattern, and the 1stpattern includes therein a 1st stress material which is different from a material forming the 1st carrier wafer, and configured to expand or shrink by thermal processing.