Carrierless Chip Package Reducing Footprint and Height
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing microelectronic device packaging methods result in large footprints and heights due to the presence of bond pads on carriers, leading to delamination issues and reduced performance, especially in space-constrained electronic products.
Innovation Solution
A carrierless chip package is developed, where an integrated circuit chip with an exposed backside surface is conductively coupled to wire bonds, which are attached to a sacrificial conductive structure, and an encapsulant material is formed around them, with the sacrificial structure being removed to expose the backside surface and conductive portions, reducing the overall package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a carrier with bond pads is used to package the integrated circuit chip, then the chip can be conductively coupled to external terminals, but the footprint and height of the packaged device increase
Solution Approach 1:
The patent removes the carrier and its bond pads from the packaging structure, extracting only the essential function of conductive coupling. The chip is directly mounted on the substrate with conductive members providing the electrical connection, eliminating the intermediate carrier structure that occupied excessive space.
Solution Approach 2:
The packaging structure is segmented into essential components only: the chip, substrate, and conductive members. Non-essential components like the carrier and its bond pads are removed, leaving a minimal structure that maintains functionality while reducing footprint.
2Reliability
If a carrier with bond pads is used to package the integrated circuit chip, then the chip can be conductively coupled to external terminals, but the height of the packaged device increases
Solution Approach 1:
The carrier structure that added vertical height is removed entirely. The conductive coupling function is achieved through direct mounting of the chip on the substrate with conductive members, eliminating the intermediate carrier layer that contributed to increased height.
Solution Approach 2:
The chip is directly mounted on the substrate in the final packaging structure, performing the conductive coupling function without requiring a separate carrier mounting step. This preliminary integration eliminates the additional height that would result from stacking the carrier on top of the substrate.
3Reliability
If large bond pads are used on the carrier, then sufficient electrical contact area is provided, but the footprint of the packaged device increases
Solution Approach 1:
Conductive members are placed locally at specific positions on the substrate where electrical contact is needed, rather than using large bond pads that occupy extensive area. This localized approach provides sufficient electrical contact while minimizing the footprint.
Solution Approach 2:
The large bond pads on the carrier are removed entirely. The electrical contact function is achieved through conductive members that provide adequate contact area without the excessive footprint associated with traditional bond pads.
4Strength
If a carrier structure is used, then mechanical support is provided, but the overall package size increases
Solution Approach 1:
The substrate serves multiple functions: it provides mechanical support for the chip, establishes electrical connections through conductive members, and acts as the packaging structure itself. This multi-functionality eliminates the need for a separate carrier, reducing overall package size.
Solution Approach 2:
The mechanical support function traditionally provided by the carrier is merged with the substrate. The substrate becomes both the mounting surface and the structural support element, eliminating redundant components and reducing package volume.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C~3A
AI summary
Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip (102) comprising an exposed backside surface (110) defining a plane, a plurality of wire bonds (106) that are conductively coupled to the integrated circuit chip (102), each of the plurality of wire bonds (106) being conductively coupled to a conductive exposed portion (108), a portion of the conductive exposed portion (108) being positioned in the plane defined by the backside surface (110), and an encapsulant material (105) positioned adjacent the integrated circuit chip (102) and the plurality of wire bonds (106).