Carry Chain Random Number Generation Using Clock Jitter
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Solution Overview
Problem
Conventional random number generators lack sufficient randomness, making it easier to predict the next number generated, which is a critical issue in applications like cryptography and encryption where unpredictability is essential.
Innovation Solution
A random number generator that utilizes a ring oscillator to produce a clock signal, which is propagated through a carry chain circuit with lookup table elements, and a detector circuit determines the stage of the clock edge, outputting 0 or 1 based on stage assignment, thereby generating a sequence with higher randomness due to unpredictable jitter effects from environmental factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional random number generation methods are used, then the device complexity is low, but the randomness and unpredictability of the generated sequence is insufficient
Solution Approach 1:
The patent converts environmental noise and jitter, which are typically considered harmful or unwanted effects, into the source of randomness for number generation. By capturing clock signal jitter caused by environmental factors and using it as entropy input, the system transforms these disturbances into beneficial random data, achieving high randomness without requiring complex external entropy sources
Solution Approach 2:
The patent introduces intermediary components including a ring oscillator to generate base clock signals, multiple carry chain circuits to propagate and differentiate clock edges, and detector circuits to capture timing variations. These intermediaries transform the raw environmental jitter into structured random number sequences, bridging the gap between physical noise and usable random data
2Reliability
If the randomness of the generated sequence is increased, then the unpredictability improves, but the difficulty of detecting and measuring the clock edge position increases
Solution Approach 1:
The patent segments the clock signal detection process into multiple independent carry chain circuits, each with its own detector circuit. By dividing the detection task across multiple parallel paths with different delay characteristics, the system can capture clock edges at different positions without requiring a single complex detection mechanism, thus maintaining ease of detection while generating unpredictable results
Solution Approach 2:
The patent uses multiple carry chain circuits with more stages than strictly necessary for a single detection path. This excessive segmentation creates multiple detection points beyond what a minimal system would require, allowing the selection of detection points based on captured jitter patterns, thereby enhancing unpredictability while keeping individual detection circuits simple
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly increases the level of randomness in the generated sequence compared to conventional random number generators, enhancing the unpredictability and security in cryptographic applications.
Implementation Method 1
the randomness in the generated sequence is a result of unpredictable jitter effects
Data Source
AI summary
An apparatus includes a carry chain circuit and a detector circuit. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates a clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.