Carry Propagate Adder for Multi-Element Comparison and Addition
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Solution Overview
Problem
Conventional data processing systems require separate circuitry for lane reduction operations, such as multi-element comparison and addition, which is resource-intensive and slow due to the need for full-word length element comparisons.
Innovation Solution
The apparatus employs non-final and final reduction stages with carry propagate adders to perform both comparison and addition operations, allowing the same hardware to be used for both tasks, with intermediate sums formatted to enable efficient execution of either operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate circuitry is provided for lane reduction operations, then both comparison and addition operations can be performed, but circuit resource consumption increases
Solution Approach 1:
The carry propagate adder circuit is designed to perform dual functions: it serves as the primary adder for addition operations and as the comparison unit for finding minimum/maximum values. By making the same hardware universal, the patent eliminates the need for separate comparison circuitry, thus reducing device complexity while maintaining versatility.
Solution Approach 2:
The patent merges the comparison function into the carry propagate adder circuit. The adder circuit incorporates comparison logic that uses the carry signals generated during addition to determine minimum and maximum values, combining what were previously separate functions into a single integrated circuit block.
2Measurement precision
If full-word length element comparisons are used, then accurate comparison can be performed, but operation speed decreases
Solution Approach 1:
The comparison operation is segmented into two phases: first, partial comparisons are performed on smaller portions of the data using the carry propagate adder, and second, the results are combined to determine the final minimum or maximum. This segmentation allows faster initial comparisons while maintaining overall accuracy through systematic combination of results.
Solution Approach 2:
The carry signals generated during the addition operation serve as intermediaries that convey comparison information. Instead of performing separate full-word comparisons, the carry propagate adder uses its internal carry logic to extract comparison results, which are then used to identify minimum and maximum values more efficiently.
Data Source
AI summary
An apparatus 8 for performing a selectable one of multi-element comparison and multi-element addition is formed from a carry propagate adders stage 12 supplied with four non-final intermediate operands formed from the input vector, a non-final limit value selecting stage 14, which when performing a multi-element comparison serves to select, in dependence upon at least carry save values generated by the carry propagate adder, limit values that are of a larger or a smaller value of a pair of elements. A final intermediate operand forming stage 16 forms final intermediate operands from two non-final intermediate sum values from the carry propagate adders stage 12 and supplies these to a final output adder stage 18 which forms a sum of these two final intermediate operands to generate an output operand which can be either one or more candidates for limit values that will be a maximum or minimum value, or a sum value, or partial sum values in the case of a multi-element addition.