Controlling Carry-Save Adder Network Width for Multiplication Speed
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Solution Overview
Problem
The existing methods for multiplying operands in data processing, such as long hand multiplication, result in a large number of partial products that need to be added together using chains of carry-save adders, leading to tight timing paths and inefficiencies.
Innovation Solution
A multiplier circuit with a controllable number of carry-save adders that reduces partial products to a redundant result value, where the number of adders used is dependent on the width of the operands, allowing for parallel processing and reduced chain lengths in the carry-save adder network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If long hand multiplication is used to multiply operands, then the multiplication can be performed systematically, but a large number of partial products are generated that require many carry-save adders, resulting in tight timing paths
Solution Approach 1:
The patent applies dynamics by making the carry-save adder network configurable and adaptive. The multiplier circuit can dynamically select between different numbers of carry-save adders (first set with 2N adders, second set with fewer than 2N adders) based on the specific multiplication operation requirements. This dynamic configuration allows the system to optimize between speed and resource usage, resolving the contradiction between multiplication speed and device complexity.
Solution Approach 2:
The patent changes the parameter of carry-save adder quantity from fixed to variable. By providing a configurable carry-save adder network that can operate with different numbers of adders (full 2N configuration or reduced configuration), the system can adjust the timing path length and computational resources based on the multiplication operands and performance requirements, thereby resolving the timing constraint issue while maintaining systematic multiplication capability.
2Manufacturing precision
If chains of carry-save adders are used to add partial products, then the partial products can be reduced to a final product, but tight timing paths are created due to the large number of adders required
Solution Approach 1:
The patent segments the carry-save adder network into multiple configurable stages and sets. Instead of using a single fixed chain of 2N carry-save adders, the system divides the addition process into segments that can be selectively activated. This segmentation allows the timing path to be broken into manageable stages, reducing the critical path delay while still achieving accurate reduction of partial products to the final product.
Solution Approach 2:
The patent applies partial action by allowing the carry-save adder network to operate with fewer than the full 2N adders in certain configurations. The second set of carry-save adders uses fewer than 2N adders, providing a reduced configuration that achieves sufficient accuracy for many multiplication operations without requiring the complete set of adders, thereby reducing timing path constraints and multiplication time.
3Productivity
If a fixed number of carry-save adders is used, then the circuit structure is simple, but the timing paths become tight and cannot be optimized for different multiplication scenarios
Solution Approach 1:
The patent implements universality by designing a carry-save adder network that can serve multiple functions and configurations within a single circuit structure. The same physical hardware can operate as a full 2N-configured network or as a reduced configuration network, adapting to different multiplication throughput requirements. This multi-functionality allows the system to optimize multiplication throughput for various scenarios without requiring separate dedicated circuits for each configuration.
Solution Approach 2:
The patent makes the carry-save adder network dynamic and reconfigurable, allowing it to adapt its structure based on operational requirements. The configurable nature enables the circuit to change its effective complexity and resource allocation dynamically, resolving the contradiction between maintaining simple fixed structure and achieving optimized performance for different multiplication scenarios through configurability.
Data Source
AI summary
A multiplier circuit is provided to multiply a first operand and a second operand. The multiplier circuit includes a carry-save adder network comprising a plurality of carry-save adders to perform partial product additions to reduce a plurality of partial products to a redundant result value that represents a product of the first operand and the second operand. A number of the carry-save adders that is used to generate the redundant result value is controllable and is dependent on a width of at least one of the first operand and the second operand.