Carry-Save MAC Unit for Feedback Loop Equalizer Latency
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Solution Overview
Problem
Conventional multiply-and-accumulate (MAC) units in digital computing devices face significant propagation delays due to the need for carry rippling during the conversion of operands from carry-save adder (CSA) format to binary format, which hampers the speed of operations in feedback loops used in high-speed equalizers and Tomlinson-Harashima precoders.
Innovation Solution
The proposed solution involves a CSA-MAC unit that operates directly in the CSA format, eliminating the need for binary conversion by using a carry-save multiplication block, 2s complement inversion block, and a carry-save adder, thereby avoiding carry rippling and reducing propagation delays. This allows the MAC unit to be integrated into timing-critical loops without converting results to binary format, and the modulo operation is performed outside the feedback loop in Tomlinson-Harashima precoders to further reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional MAC units convert operands from carry-save adder format to binary format, then the addition operation can be performed in standard binary format, but propagation delays increase due to carry rippling
Solution Approach 1:
The patent segments the addition operation into two independent parts: a sum portion and a carry portion, both maintained in carry-save adder format. This segmentation avoids the need for carry propagation through the entire bit width, eliminating the time-consuming carry rippling process while allowing parallel processing of sum and carry bits.
Solution Approach 2:
Instead of converting from carry-save format to binary format (the conventional approach), the patent inverts the approach by performing multiplication and accumulation directly in carry-save format. This inversion eliminates the conversion step that causes carry rippling delays, maintaining operations in the non-standard format throughout the critical feedback loop.
2Ease of operation
If conventional MAC units perform binary conversion, then standard binary format operations are enabled, but power consumption increases
Solution Approach 1:
The patent extracts the binary conversion step from the critical feedback loop operation path. By maintaining carry-save format throughout the multiplication and accumulation operations, the conversion to binary format is removed from the time-critical and power-critical path, reducing both propagation delay and power consumption while still enabling binary output when needed for final results.
3Reliability
If modulo operation is performed inside the feedback loop, then complete Tomlinson-Harashima precoding is achieved, but feedback loop delay increases
Solution Approach 1:
The patent performs preliminary actions by completing the multiplication and accumulation operations in carry-save format before the modulo operation is required. The carry-save format maintains the numerical results in a usable state throughout the feedback loop, allowing the modulo operation to be deferred without losing precision or introducing errors, thereby reducing feedback loop delay while maintaining precoding accuracy.
Data Source
AI summary
A multiply and accumulation (MAC) unit for multiplying a provided first and a provided second multiplicand and for adding a provided summand to the resulting product is described. The MAC includes at least one multiplication block which is configured to multiply a first input signal and a second input signal, wherein the first input signal is given in a carry-save adder format and the second input signal is given in a binary format, wherein the multiplication result is provided in a carry-save format, and a carry-save adder which is configured to add to the result of the multiplication the provided summand.