Carryless Multiplier CRC32 for Low-Latency Error Checking

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing CRC calculation methods, such as linear feedback shift registers, are slow and fail to meet latency requirements in applications like cryptography, where larger data sizes necessitate faster error detection.

Innovation Solution

Implementing CRC32 instructions using a carryless multiplier, which enables faster CRC calculations by performing carryless operations and accumulating CRC values within a microcircuit, reducing latency from 64 cycles to approximately 3 cycles for 64-bit inputs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a linear feedback shift register network is used for CRC calculation, then the implementation is simple and reliable, but the calculation speed is slow and latency is high

Engineering Contradiction:

ImproveCRC calculation speedVSAvoidCRC calculation latency

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent replaces the sequential mechanical shifting operation of LFSR with a parallel carryless multiplication operation. The CRC calculation is transformed from a time-consuming bit-by-bit shift process into a single-cycle or few-cycle polynomial multiplication operation, achieving approximately 20-fold speed improvement and reducing latency from 64 clock cycles to about 3 clock cycles for 64-bit inputs.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the computational parameters by representing the input data as a polynomial and performing carryless multiplication with the generator polynomial. This parameter transformation allows the CRC calculation to be completed in constant time regardless of input size, fundamentally changing the time complexity from linear to constant.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If a linear feedback shift register network is used for CRC calculation, then the implementation is straightforward, but the latency does not meet requirements for cryptographic applications with large data sizes

Engineering Contradiction:

ImproveCRC calculation throughputVSAvoidCRC calculation latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent substitutes the sequential LFSR mechanism with a parallel carryless multiplication unit, enabling simultaneous processing of all input bits. This substitution increases productivity by approximately 20 times while reducing latency to constant time, meeting the requirements for cryptographic applications handling large data sizes.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent performs preliminary setup by pre-computing and storing the carryless multiplication constants and polynomial coefficients in lookup tables or hardwired logic. This preliminary action enables the actual CRC calculation to be executed in constant time without sequential processing, significantly improving throughput and reducing latency.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8977943B2Implementation of CRC32 using carryless multiplier

Publication Date: 2015.03.10 ADVANCED MICRO DEVICES INC

AI summary

Methods, apparatus, and fabrication processes relating to implementing cyclic redundancy checks (CRCs) in processors, such as CRC32 instructions in x86 computer architectures. A method may comprise extracting a first CRC value from a data packet, performing a carryless operation upon the data packet to determine a second CRC value, and determining that a data error is present in the data packet when the first and second CRC values do not match.