Carry-Less Multiplication Hashing for Fast 128-Bit Quality

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Solution Overview

Problem

Existing non-cryptographic hashing algorithms are either computationally complex or of limited size and quality, failing to meet throughput and latency goals, while cryptographic hashes are too complex for high-speed applications.

Innovation Solution

A three-stage hashing process using carry-less multiplication and modern CPU instructions to generate high-quality, 128-bit hashes, leveraging CRC technology for speed and quality, with init, update, and finalize stages optimized for parallel processing and reduced latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cryptographic hash algorithms (SHA, MD5, SM3) are used, then hash quality is improved, but computational complexity increases making them too slow to meet throughput and latency goals

Engineering Contradiction:
Improvehash qualityVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces expensive cryptographic hash operations with cheaper non-cryptographic hash functions that provide sufficient quality for non-security applications. The invention uses simple polynomial rolling hash computations instead of complex cryptographic algorithms, achieving acceptable hash quality at much lower computational cost.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the parameters of the hash function by using 64-bit integers and polynomial rolling computations with configurable prime moduli, rather than fixed cryptographic algorithm parameters. This allows tuning of hash quality versus speed trade-offs by selecting different polynomial degrees and prime values.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If non-cryptographic hash functions are used, then computational speed is improved, but hash quality and size are limited to 32-64 bits

Engineering Contradiction:
Improvecomputational speedVSAvoidhash quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from traditional 32-64 bit hash outputs to 128-bit hash values by performing polynomial rolling computations on 64-bit integers and combining results. This dimensional expansion in the hash output space provides both higher quality and reduced collision probability while maintaining computational efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the input data into fixed-size blocks and processes each block through polynomial rolling hash computations, then combines the results to produce the final 128-bit hash. This segmentation approach maintains speed while achieving higher quality through the combination of multiple computation results.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If traditional integer arithmetic hashing is used, then implementation simplicity is improved, but hash quality and collision resistance are limited

Engineering Contradiction:
Improveimplementation simplicityVSAvoidcollision resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent combines multiple integer arithmetic operations (polynomial rolling, modular arithmetic with prime moduli, and 64-bit integer computations) into a composite hashing approach. This composite method maintains the simplicity of integer arithmetic while achieving superior collision resistance through the combination of multiple computational steps.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS12621124B2Non-cryptographic hashing using carry-less multiplication
Publication Date: 2026.05.05 INTEL CORP
  • US12621124B2 patent drawing
  • US12621124B2 patent drawing
  • US12621124B2 patent drawing

AI summary

Non-cryptographic hashing using carry-less multiplication and associated methods, software, and apparatus. Under one aspect, the disclosed hash solution expands on CRC technology that updates a polynomial expansion and final reduction, to use initialization (init), update and finalize stages with extended seed values. The hash solutions operate on input data partitioned into multiple blocks comprising sequences of byte data, such as ASCII characters. During multiple rounds of an update stage, operations are performed on sub-blocks of a given block in parallel including carry-less multiplication and shuffle operations. During a finalize stage, multiple SHA or carry-less multiplication operations are performed on data output following a final round of the update stage.