Carryless Multiplication Preformat Unit for Microprocessors
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Solution Overview
Problem
Current microprocessor designs lack a unit capable of performing carryless multiplication, as existing hardware is unsuitable due to the generation and propagation of carry bits during ordinary multiplication operations, necessitating separate and resource-intensive hardware for carryless operations.
Innovation Solution
A method and apparatus that utilize existing Booth encoding hardware by partitioning operands into even and odd portions, preventing selection of partial products that introduce carries, and employing a modified compressor to enable carryless multiplication within a microprocessor, allowing for minimal hardware modifications and shared use of existing hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing multiplication hardware is used for carryless multiplication, then hardware resource utilization improves, but the generation and propagation of carry bits causes incorrect results
Solution Approach 1:
The first operand is partitioned into even and odd portions, where even portions are used to generate partial products that do not introduce carries, and odd portions are handled separately. This segmentation allows the Booth encoder to select only from carry-free partial products, resolving the contradiction between using existing hardware and preventing carry propagation.
Solution Approach 2:
A carryless preformat unit is introduced as an intermediary component between the operand input and the Booth encoder. This unit preprocesses the first operand by partitioning it into even and odd portions, enabling the existing Booth encoding hardware to operate correctly for carryless multiplication without direct modification to the core multiplication logic.
2Reliability
If separate hardware is designed for carryless multiplication, then correctness of results improves, but device footprint and power consumption increase
Solution Approach 1:
The existing Booth encoding and compression hardware is made universal to handle both ordinary and carryless multiplication operations. By introducing the preformat unit that partitions the first operand into even and odd portions, the same hardware resources can be configured for different multiplication modes, eliminating the need for separate dedicated carryless multiplication hardware and thus reducing device footprint.
3Productivity
If Booth encoding is used to reduce partial products, then multiplication speed improves, but carry bits are generated and propagated
Solution Approach 1:
The carryless preformat unit performs preliminary action by partitioning the first operand into even and odd portions before the Booth encoding process. This preprocessing ensures that when the Booth encoder generates partial products, only those from even portions (which do not introduce carries) are selected, thereby eliminating carry bit generation while maintaining the speed benefits of Booth encoding.
Data Source
AI summary
An apparatus is provided for performing carryless multiplication. The apparatus has an opcode dectector and a carryless preformat unit. The opcode dectector is configured to receive a carryless multiplication instruction, and is configured to assert a carryless signal responsive to receipt of the carryless multiplication instruction. The carryless preformat unit is configured to partition the first operand into parts responsive to assertion of the carryless signal, where the parts are configured such that a Booth encoder selects first partial products corresponding to a second operand and is precluded from selection of second partial products corresponding to the second operand, and where the second partial products are results of implicit carry operations. The first partial products are exclusive-ORed together to yield a carryless multiplication result.