Carryless Multiplication Unit Using Preformat and XOR Logic
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Solution Overview
Problem
Current microprocessor designs lack a unit capable of performing carryless multiplication efficiently, as existing hardware is unsuitable due to the generation and propagation of carry bits, necessitating separate hardware that increases power consumption and complicates debugging.
Innovation Solution
A carryless multiplication unit is designed using existing Booth encoding and compression hardware, preformatting operands to prevent implicit carry operations, employing a carryless preformat unit, Booth encoder, compressor, left shifter, and exclusive-OR logic to execute carryless multiplication without generating carry bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate hardware is designed for carryless multiplication, then carryless multiplication capability is achieved, but power consumption increases and device footprint expands
Solution Approach 1:
The patent makes the existing multiplication unit perform both ordinary multiplication and carryless multiplication by adding a preformat unit that transforms operands before they enter the existing Booth encoder and compressor. This allows one hardware unit to serve multiple functions without requiring separate dedicated hardware for carryless multiplication.
Solution Approach 2:
The preformat unit performs preliminary transformation of the multiplier operand by inserting zero bits at specific positions before the multiplication operation. This pre-processing step modifies the input data format to prevent implicit carry generation during subsequent Booth encoding, enabling carryless multiplication using existing hardware designed for ordinary multiplication.
2Adaptability or versatility
If separate hardware is designed for carryless multiplication, then carryless multiplication capability is achieved, but device footprint and complexity increase
Solution Approach 1:
The multiplication unit is enhanced to handle both ordinary and carryless multiplication operations through a single integrated design. The preformat unit adds minimal complexity while enabling the existing Booth encoder and compressor to perform carryless multiplication, avoiding the need for separate dedicated hardware units.
Solution Approach 2:
By performing the carryless multiplication transformation in advance through the preformat unit, the patent avoids the need for complex alternative hardware designs. The pre-processing step simplifies the overall architecture by preparing inputs in a format that the existing multiplication unit can handle directly.
3Ease of manufacture
If existing multiplication hardware is used for carryless multiplication, then hardware reuse is maximized, but implicit carry operations must be prevented
Solution Approach 1:
The preformat unit performs preliminary transformation of the multiplier operand by inserting zero bits at positions that would otherwise generate implicit carries during Booth encoding. This pre-processing prevents the harmful carry operations before they can occur in the existing multiplication hardware.
Solution Approach 2:
The patent converts the potential harm of implicit carry operations into a benefit by using the Booth encoder's existing structure. By carefully formatting the input operands with zero bits inserted at critical positions, the existing carry-propagating hardware is made to naturally produce carryless results through the modified input pattern.
4Productivity
If Booth encoding is used to reduce partial products, then multiplication speed is improved, but carry bits are generated and propagated
Solution Approach 1:
Before Booth encoding is applied, the preformat unit transforms the multiplier operand by inserting zero bits at specific positions. This preliminary action ensures that when Booth encoding subsequently processes the formatted operand, the encoding process naturally avoids generating implicit carry bits, thus maintaining high multiplication speed without the harmful side effect of carry propagation.
Data Source
AI summary
An apparatus having a carryless preformat unit, a Booth encoder, a compressor, a left shifter, and exclusive-OR logic. The carryless preformat unit receives a multiplier operand and partitions the multiplier operand into parts. The Booth encoder receives the parts and directs selection of first partial products of a multiplicand that do not reflect implicit carry operations. The compressor sums the first partial products via a configuration of carry save adders that generate sum bits and carry bits, where generation of the carry bits is disabled during execution of the carryless multiplication. The left shifter shifts bits of one or more outputs of the compressor. The exclusive-OR logic is coupled to the compressor and the left shifter, and is configured to execute an exclusive-OR function on the outputs to yield a carryless multiplication result.