Deadlock-Free Routing in Cartesian Topologies via Minimal Virtual Lanes

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Solution Overview

Problem

Existing network communication systems in Cartesian topologies, such as mesh and torus, face deadlocks due to cyclic dependencies in switch buffers, which traditional methods like Dimension Ordered Routing (DOR) cannot address effectively, especially in flexible routing scenarios and when dealing with faulty switches or links.

Innovation Solution

The implementation of a network management system that allows routes to traverse dimensions both in and opposite to the predefined order, using multiple Virtual Lanes (VLs) to prevent deadlocks, and a Breadth First Search (BFS) method to select routes with a minimal number of 'opposite turns' to minimize VLs required, ensuring deadlock-free and adaptive routing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If traditional Dimension Ordered Routing (DOR) is used in Cartesian topologies, then routing simplicity is maintained, but deadlock conditions occur due to cyclic dependencies in switch buffers

Engineering Contradiction:
Improverouting simplicityVSAvoiddeadlock freedom
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent segments the routing space by dividing it into multiple regions based on the source-destination pair coordinates. Each region has its own predefined route, preventing cyclic dependencies across the entire network while maintaining simplicity within each segment. This segmentation approach breaks the global cyclic dependency that causes deadlocks in traditional DOR.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of allowing free routing and preventing deadlocks through complex control mechanisms, the patent inverts the approach by predefining restricted routes for each region. This inversion transforms the problem from active deadlock prevention to passive deadlock avoidance through careful route design, eliminating cyclic dependencies while maintaining routing simplicity.

Inventive Principle:
Principle #13The other way round (Inversion)

2Adaptability or versatility

If flexible routing paths are allowed to handle faulty switches or links, then network adaptability improves, but deadlock conditions become more likely due to increased routing options

Engineering Contradiction:
Improvenetwork adaptabilityVSAvoiddeadlock freedom
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies local quality by assigning different routing characteristics to different regions of the network. Each region has routes specifically optimized for its local topology and fault conditions, allowing flexible adaptation to local failures while maintaining global deadlock freedom through the coordinated design of all regional routes.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The routing system dynamically selects appropriate predefined routes based on the current source-destination pair and detected fault conditions. This dynamic selection among multiple predefined routes provides adaptability to faults while maintaining deadlock freedom, as all routes are designed to avoid cyclic dependencies.

Inventive Principle:
Principle #15Dynamics

3Reliability

If multiple Virtual Lanes (VLs) are used to prevent deadlocks, then deadlock freedom is achieved, but device complexity increases

Engineering Contradiction:
Improvedeadlock freedomVSAvoidVirtual Lane management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the deadlock prevention mechanism from complex Virtual Lane management and embeds it directly into the route selection logic. By integrating deadlock prevention into the routing algorithm itself, the system eliminates the need for separate VL management complexity while maintaining deadlock freedom through the predefined regional routes.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP3328008B1Deadlock-free routing in lossless multidimensional cartesian topologies with minimal number of virtual buffers
Publication Date: 2020.01.01 MELLANOX TECH TLV
  • EP3328008B1 patent drawingFigure 1~2
  • EP3328008B1 patent drawingFigure 3
  • EP3328008B1 patent drawingFigure 4

AI summary

An apparatus (36) includes a network interface (28) and a processor (40). The network interface is configured to communicate with a network that includes a plurality of switches (32) interconnected in a Cartesian topology having multiple dimensions. The processor is configured to predefine an order among the dimensions of the Cartesian topology, to search for a preferred route via the network from a source switch to a destination switch, by evaluating candidate routes based at least on respective numbers of switches along the candidate routes for which traversal to a next-hop switch changes from one of the dimensions to another of the dimensions opposite to the predefined order, and to configure (124) one or more of the switches in the network to route packets from the source switch to the destination switch along the preferred route.