Carved Probe Metrology for Lithography-Free 2D Semiconductor Screening
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Solution Overview
Problem
The transition of 2D layered semiconductors from lab to fab is hindered by the lack of effective characterization methods for screening key physical properties such as material quality, uniformity, and electrical properties in mass-produced devices.
Innovation Solution
A system with an apparatus that uses carved probes to rapidly extract electrical properties like resistivity from 2D materials, allowing for the measurement of current-voltage characteristics without additional lithography steps, and enabling automation and wafer-scale applicability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional lithography-based characterization methods are used, then measurement precision can be achieved, but device complexity and manufacturing time increase significantly
Solution Approach 1:
The patent extracts the lithography step from the characterization process by using a pre-formed probe card with carved probes that directly contact the 2D material. This eliminates the need for complex lithography-based patterning while maintaining measurement capability, directly resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The patent replaces the mechanical lithography process with a direct mechanical probing system. The carved probes physically contact and measure the 2D material without requiring prior lithographic patterning, substituting a simpler mechanical measurement system for the complex lithography-based approach
2Measurement precision
If conventional characterization methods with multiple processing steps are used, then comprehensive property screening is achieved, but productivity and measurement speed decrease
Solution Approach 1:
The probe card is pre-configured with multiple carved probes of different geometries (varying widths, lengths, and aspect ratios) before contact with the sample. This preliminary preparation allows simultaneous measurement of multiple electrical properties in a single contact event, eliminating sequential processing steps and significantly improving productivity while maintaining comprehensive screening capability
Solution Approach 2:
The patent merges multiple measurement functions into a single probe card structure. Different carved probes on the same card can simultaneously measure resistivity, sheet resistance, and other electrical properties, combining what would traditionally require multiple separate measurement steps into one operation, thereby increasing measurement speed without sacrificing comprehensive property screening
3Measurement precision
If additional lithography steps are performed for pattern formation, then measurement accuracy improves, but loss of time and manufacturing cost increase
Solution Approach 1:
The patent removes the lithography step entirely from the measurement process. The carved probes are pre-formed with precise geometries that directly contact the 2D material to enable accurate electrical measurements without requiring any lithographic patterning of the sample, thus eliminating the time loss associated with lithography while maintaining measurement precision
Solution Approach 2:
Instead of creating patterns through lithography on the sample, the patent uses pre-carved probe geometries that copy the desired measurement patterns. The probe card contains multiple copies of different probe geometries that can be used to measure various electrical characteristics without modifying the sample through lithography, saving time while preserving measurement accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables rapid, automated, and lithography-free characterization of electrical properties in 2D layered semiconductors, facilitating the early screening of electrical parameters and supporting the integration of 2D materials into high-volume manufacturing.
Implementation Method 1
pushing the respective punching tips of the plurality of members of the testing apparatus against the semiconductor substrate; carving a plurality of stripe shapes along the semiconductor substrate
Implementation Method 2
measuring at least one electrical property of the semiconductor substrate along at least one stripe of the plurality of stripe shapes
Data Source
AI summary
An apparatus includes a body and a plurality of members extending from the apparatus configured to form carvings with different geometries along 2D layered semiconductor material. The apparatus includes conductive pins positioned along the plurality of members that accommodate individual sensing of current-voltage characteristics per carving. The carvings can include small stripes and the apparatus can probe the electrical resistance of the small stripes of 2D layered semiconductors where the geometry defines strong current confinement, thus enabling the rapid extraction of sheet resistance for rapid comparison between material quality.