CAS Latency Circuit DLL Phase Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed semiconductor memory devices face challenges in generating a stable latency signal due to increasing external clock frequencies, which reduce the margin between the internal read command signal and the output clock, leading to improper latching and inaccurate CAS latency counting.
Innovation Solution
A CAS latency circuit that includes an internal read command signal generator, a latency control clock generator using a delay lock loop (DLL) to generate latency control clocks with an absolute margin, and a latency signal generator that shifts the internal read command signal based on these clocks, ensuring stable latching and data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the external clock frequency is increased to achieve high-speed operation, then the processing speed improves, but the margin between the internal read command signal and the output clock reduces, causing improper latching
Solution Approach 1:
The patent applies preliminary action by generating the latency control clock signal in advance with a predetermined phase advance relative to the output clock signal. This phase advance is established before the read command is processed, ensuring that the latency signal can be properly latched even at high clock frequencies where the timing margin would otherwise be insufficient.
Solution Approach 2:
The patent implements dynamics by making the latency control clock signal phase adjustable and adaptive. The phase of the latency control clock is dynamically controlled to maintain the appropriate timing relationship between the internal read command signal and the output clock, allowing the system to adapt to varying operating conditions and maintain reliable latching across different speeds.
2Productivity
If the external clock frequency is increased, then the data throughput improves, but the phase margin and timing stability deteriorate under variations in pressure, voltage, and temperature
Solution Approach 1:
The patent applies feedback by using the delay-locked loop (DLL) circuit to continuously monitor and adjust the phase of the latency control clock signal. The DLL circuit receives the output clock signal, generates a delayed version, and uses feedback control to maintain the predetermined phase relationship, compensating for variations caused by pressure, voltage, and temperature changes to ensure stable timing.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the phase parameter of the latency control clock signal through the DLL circuit. This allows the system to maintain optimal timing characteristics across varying operating conditions by changing the phase parameter in response to environmental variations, thereby preserving timing stability despite changes in pressure, voltage, and temperature.
3Device complexity
If conventional signal delay units are used to generate latency control clocks, then the circuit complexity is low, but the frequency margin is insufficient for high-speed operation
Solution Approach 1:
The patent introduces an intermediary element - the delay-locked loop (DLL) circuit - that mediates between the output clock signal and the latency control clock signal. This intermediary DLL circuit provides the necessary phase control and frequency margin enhancement without requiring a complete redesign of the entire timing system, achieving high-speed operation with moderate complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a stable latency signal in high-speed semiconductor memory devices, maintaining proper latching and data output even with increased external clock frequencies and variations in pressure, voltage, and temperature, offering a frequency margin twice that of conventional devices.
Implementation Method 1
a latency control clock generator configured to generate a latency control clock signal based on a clock signal, the latency control clock signal having a predetermined phase advanced from a phase of an output clock signal
Data Source
AI summary
Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.