Cascadable Instant-Fall-Through FIFO Buffer Design

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Solution Overview

Problem

High-speed data processing systems require faster FIFO buffers to minimize propagation delays caused by multiplexers and counters, which slow down data streaming due to the need for additional combinational logic.

Innovation Solution

A cascadable, instant-fall-through FIFO buffer design that eliminates the need for multiplexers and counters by using a series of buffer slices with control bit registers to shift data directly to the output slice, reducing combinational logic and enabling faster data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional FIFO buffer design using multiplexers and counters is used, then the buffer can store and manage data, but propagation delays increase and processing speed decreases

Engineering Contradiction:

Improvedata processing speedVSAvoidcombinational logic complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The FIFO buffer is divided into multiple independent buffer slices, each with its own data register and control bit register. This segmentation eliminates the need for complex global multiplexers and counters, reducing combinational logic and propagation delays while maintaining the buffering function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent removes the multiplexer and counter components from the traditional FIFO design. By extracting these complex combinational logic elements and replacing them with simple buffer slices and control bit registers, the design achieves faster operation without the propagation delays inherent in multiplexer-based architectures.

Inventive Principle:

Principle #2Taking out (Extraction)

2Quantity of substance

If buffer depth is increased to store more data, then storage capacity improves, but propagation delays increase and performance degrades

Engineering Contradiction:

Improvedata storage capacityVSAvoiddata processing speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

By segmenting the buffer into multiple slices that can operate independently, the system can increase total storage capacity by adding more slices without increasing the propagation delay within each slice. Each slice maintains simple logic regardless of overall buffer depth.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimensional array structure to a multi-dimensional structure with multiple buffer slices organized in a cascaded configuration. This dimensional change allows data to flow through multiple parallel paths, reducing the effective propagation delay even as total capacity increases.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7979607B2Cascadable high-performance instant-fall-through synchronous first-in-first-out (FIFO) buffer

Publication Date: 2011.07.12 HONEYWELL INTERNATIONAL INC

AI summary

An apparatus and method of operating a cascadable, instant-fall-through First In, First Out (FIFO) buffer is provided. The method comprises receiving a first data element at an input of a FIFO buffer which includes a plurality of buffer slices including an output buffer slice wherein each of the plurality of buffer slices comprise a data register and a control bit register. A buffer slice is identified which is indicated for storing a data element based on a control bit register for the buffer slice and a control bit register of an adjacent buffer slice on an output side. When data is read from an output buffer slice the FIFO buffer, all data in other buffer slices are shifted down one slice closer to the output side of the FIFO buffer.