Cascade Comparator Clocking Without Hold Switch Glitches
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Solution Overview
Problem
In multi-stage comparator systems used in analog-to-digital converters, the inclusion of a hold switch to maintain signal levels between stages increases circuit size and power consumption, and can interfere with linear operation due to glitches.
Innovation Solution
Adjusting clock signals to partially overlap the regeneration phases of comparator stages, eliminating the need for a hold switch by ensuring that subsequent stages regenerate before preceding stages reset, thus maintaining signal integrity without additional circuit components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hold switch is provided between comparator stages to maintain signal levels, then the reliability of output data is improved, but the circuit size increases and power consumption increases
Solution Approach 1:
The patent removes the hold switch component from the circuit by implementing a hold-free cascade comparator structure. The clock signal control mechanism replaces the hold switch function, allowing the circuit to maintain signal levels through coordinated clocking of comparator stages rather than through a separate holding component.
Solution Approach 2:
The clock signal serves multiple functions: it triggers comparator operation, controls the timing of signal transfer between stages, and implicitly maintains signal levels during critical periods. This multi-functionality eliminates the need for dedicated hold switch components while achieving the same reliability effect.
2Reliability
If a hold switch is provided between comparator stages to maintain signal levels, then the reliability of output data is improved, but the power consumption increases
Solution Approach 1:
The patent removes the hold switch component from the circuit by implementing a hold-free cascade comparator structure. The clock signal control mechanism replaces the hold switch function, allowing the circuit to maintain signal levels through coordinated clocking of comparator stages rather than through a separate holding component.
Solution Approach 2:
The clock signal serves multiple functions: it triggers comparator operation, controls the timing of signal transfer between stages, and implicitly maintains signal levels during critical periods. This multi-functionality eliminates the need for dedicated hold switch components while achieving the same reliability effect.
3Stability of the object's composition
If a hold switch is provided between comparator stages to maintain signal levels, then the stability of cascading is improved, but glitches are introduced that interfere with linear operation
Solution Approach 1:
The patent removes the hold switch component from the circuit by implementing a hold-free cascade comparator structure. The clock signal control mechanism replaces the hold switch function, allowing the circuit to maintain signal levels through coordinated clocking of comparator stages rather than through a separate holding component.
Solution Approach 2:
The clock signal is designed to advance the operation of subsequent comparator stages before previous stages complete their cycles. This preliminary action ensures that signal levels are maintained through proper timing coordination rather than through hold switches that introduce glitches.
Data Source
AI summary
A cascade comparator and a control method thereof are provided. By applying multi-phase clock signals to a plurality of comparators when the plurality of comparators are cascaded together so that each comparator is regenerated before the preceding comparator is reset, a hold switch does not need to be provided between the comparators. Therefore, it is possible to reduce the size and parasitic components of a circuit, operate the circuit at a high speed, remove a glitch caused by any hold switch, and accordingly improve system linearity.