Cascade Control Chips Error Sharing via Watchdog OR Signal
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Solution Overview
Problem
In inkjet recording systems with multiple control chips, existing monitoring methods struggle to effectively share and manage errors, particularly when a CPU fails to control the recording head and motor, leading to system failures, as they rely on communication between chips which can be disrupted by errors like static electricity or watchdog timer resets.
Innovation Solution
The electronic apparatus features cascade-connected control chips with a watchdog timer and a transfer unit that generates an OR signal from both the local and downstream watchdog timers' interrupt signals, allowing error sharing among upstream chips, enabling safe system shutdown or reactivation without immediate CPU intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single watchdog timer monitors multiple controllers, then the device complexity is reduced, but the reliability of error detection deteriorates because communication disruptions may cause false error detection
Solution Approach 1:
The patent divides the monitoring function into multiple watchdog timers, with each controller having its own dedicated watchdog timer. This segmentation allows each watchdog to independently monitor its corresponding controller without being affected by communication disruptions between controllers, thereby maintaining high reliability while managing complexity through modular design.
Solution Approach 2:
The patent introduces an error information sharing mechanism as an intermediary between the multiple watchdog timers and controllers. When a watchdog detects an error, it shares this information with other controllers through the intermediary mechanism, enabling coordinated error response without requiring direct communication between controllers that could be disrupted by static electricity or other interference.
2Reliability
If error information is shared among all controllers, then the system can respond more appropriately to errors, but the device complexity increases due to additional communication and coordination mechanisms
Solution Approach 1:
The patent merges the error detection and error response functions into an integrated system. Each watchdog timer not only detects errors but also shares error information with other controllers, and the error response mechanism is combined with the existing controller architecture. This merging reduces the need for separate complex error management subsystems while maintaining comprehensive error handling capability.
Solution Approach 2:
The patent implements a self-service error response mechanism where each controller can independently respond to errors based on shared error information without requiring complex centralized coordination. When error information is shared, each controller autonomously determines and executes appropriate responses, reducing the complexity of inter-controller coordination while maintaining reliable error handling.
Data Source
AI summary
In an electronic apparatus in which a plurality of controller chips are cascade-connected, if an error occurs in a given chip, the present invention allows at least chips on the upstream side of the error chip to share the existence of the error chip. The electronic apparatus of this invention includes a plurality of control chips which are cascade-connected. Each control chip includes a watchdog timer, and a transfer unit configured to supply, to a second another control chip positioned on the upstream side, as an interrupt signal from the watchdog timer, an OR signal of an interrupt signal generated by the watchdog timer and an interrupt signal generated by another watchdog timer in a first another control chip positioned on the downstream side.