Cascade Gate Driver Layout for Low-Power Multi-Zone Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional gate drivers for display devices, such as LCDs and OLEDs, have large layout areas and high power consumption due to the numerous transistors and signal inputs required, making them unsuitable for narrow or borderless display panels.
Innovation Solution
A gate driver design that uses a cascade-connected configuration with a latch circuit and output circuit, comprising transistors and a capacitor, to reduce the number of components and input signals, allowing for adaptive scan functions across multiple display zones, thereby minimizing layout area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional gate driver designs are used, then the gate driver can perform scan functions, but the layout area and power consumption are large
Solution Approach 1:
The gate driver is divided into multiple stages, with each stage containing a latch circuit and an output circuit. This segmentation allows each stage to be independently optimized and reduces the overall complexity, thereby reducing layout area while maintaining scan function capability.
Solution Approach 2:
The patent extracts and eliminates redundant transistors and signal inputs from conventional gate driver designs. By removing unnecessary components while retaining essential scan functions, the layout area is significantly reduced without compromising functionality.
2Use of energy by stationary object
If conventional gate driver designs are used, then the gate driver can perform scan functions, but the power consumption is high
Solution Approach 1:
The patent removes redundant transistors and signal paths from conventional gate driver designs. By extracting only the essential components needed for scan functions, power consumption is reduced while maintaining full scan capability.
Solution Approach 2:
The patent optimizes the electrical parameters of the remaining components, such as transistor sizing and signal timing, to minimize power consumption while ensuring reliable scan function operation across all display zones.
3Area of stationary object
If the gate driver uses fewer components, then the layout area is reduced, but the reliability may be compromised
Solution Approach 1:
By dividing the gate driver into modular stages with standardized latch and output circuits, the patent achieves compact layout while maintaining reliability through modular design. Each module can be independently verified and replaced if needed.
Solution Approach 2:
The patent carefully optimizes the parameters of the reduced component set, such as transistor dimensions and signal timing, to ensure that reliability requirements are met despite using fewer components overall.
4Adaptability or versatility
If the gate driver is designed for multi-zone display devices, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The patent designs the gate driver with universal latch and output circuits that can operate across multiple display zones. Each stage can be configured to drive different zones, providing adaptability without requiring separate circuit designs for each zone.
Solution Approach 2:
By segmenting the gate driver into reusable stages, the patent achieves multi-zone adaptability through replication of standardized modules rather than designing complex unique circuits for each zone, thereby reducing overall device complexity.
Data Source
AI summary
A gate driver comprises an ith stage gate driver circuit including a latch circuit and a first output circuit. The latch circuit includes a first input for receiving an (i−1)th gate signal, a second input for receiving a first clock signal, a first output for outputting a first output signal, and a second output for outputting a second output signal. The first output circuit comprises a first transistor, a second transistor and a capacitor. The first transistor includes a control terminal coupled to the first output, a first terminal coupled to a first clock input and a second terminal coupled to a first output node. The second transistor includes a control terminal coupled to the second output, a first terminal coupled to the first output node and a second terminal coupled to a reference signal. The capacitor is coupled between the first transistor and the first output node.