Cascade Integrator ADC Transfer Shaping for Faster Conversion

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Solution Overview

Problem

Conventional integral analog-to-digital converters (ADCs) have a slow conversion rate due to their working principle, and previous attempts to improve this by altering the reference voltage waveform are complex, difficult to expand, and result in poor linearity of the transfer characteristic.

Innovation Solution

A cascade N-stage integrator structure is used, where each integrator consists of a resistor, capacitor, operational transconductance amplifier, and switch, with the output of each integrator connected to the input of the next, resulting in a voltage change proportional to time to the power of N, improving the conversion efficiency and linearity of the ADC.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the reference voltage waveform is changed to improve conversion rate, then the conversion rate increases, but the linearity of transfer characteristic deteriorates

Engineering Contradiction:
Improveconversion rateVSAvoidlinearity of transfer characteristic
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent divides the single integrator into multiple cascaded integrator stages. Each integrator processes the signal sequentially, with the output of one feeding into the next. This segmentation allows the system to achieve higher conversion rates through the polyphase structure while maintaining linearity through the controlled cascaded integration process, resolving the contradiction between speed and accuracy.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the reference voltage waveform is altered to increase conversion rate, then the conversion rate improves, but the system complexity increases

Engineering Contradiction:
Improveconversion rateVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent creates multiple copies of the integrator circuit arranged in a cascaded structure. Rather than designing a completely new complex waveform generation system, it replicates the basic integrator unit multiple times and connects them in sequence. This copying approach increases conversion rate through the polyphase structure while keeping each individual stage simple and manageable, thus improving productivity without excessive complexity increase.

Inventive Principle:
Principle #26Copying

3Device complexity

If conventional integrator or DAC is used to generate reference voltage, then the structure is simple, but the conversion rate is slow

Engineering Contradiction:
Improvestructure simplicityVSAvoidconversion rate
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent transforms the static single-integrator structure into a dynamic multi-stage cascaded system. The reference voltage is generated dynamically through the sequential operation of multiple integrator stages, each contributing to the overall conversion process. This dynamic structure enables faster conversion rates compared to the static conventional approach, while maintaining structural simplicity through the regular cascaded configuration of identical stages.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10673448B2System and method for regulating transfer characteristics of integral analog-to-digital converter
Publication Date: 2020.06.02 SHANGHAI INTEGRATED CIRCUIT RESEARCH & DEVELOPMENT CENTER CO LTD
  • US10673448B2 patent drawing
  • US10673448B2 patent drawing
  • US10673448B2 patent drawing

AI summary

A system and method for regulating transfer characteristics of an integral analog-to-digital converter are provided. The system comprises a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein, the N is positive integer greater than or equal to 2. In the cascade multistage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N. By adopting a cascade multistage integrator according to the present disclosure, it is simple to regulate transfer characteristics of the ADC, and the cascade digital signal processing is convenient, which can reduce the ADC conversion time and improve the ADC conversion rate. Compared with the existing polyline mode, the present disclosure has better linearity; and it can be easily extended to cascade multistage integrators.