Cascade Level Shifter Circuit for Thin-Oxide Overvoltage Protection
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Solution Overview
Problem
Existing level shifters produce extreme output voltages that can cause overvoltage stress and higher leakage currents in thin oxide field effect transistors, leading to unwanted feedback paths and reliability issues, particularly in 14 nm and 10 nm technologies where thick oxide FETs are not available.
Innovation Solution
A level shifter circuit using a resistor divider string and cascaded inverters formed by P-channel and N-channel field effect transistor pairs, connected between an analog voltage rail and ground, which steps voltage up between tap points and limits output levels to prevent overvoltage conditions, utilizing thin oxide FETs for effective voltage translation and overvoltage protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current level shifters translate VDD logic signals to Analog VDD voltages with output voltages between 0 volts and AVDD volts, then voltage translation is achieved, but overvoltage stress occurs on transmission gate or pass gate devices and connected Analog multiplexer
Solution Approach 1:
The patent changes the output voltage parameters by introducing a resistor divider network that scales down the AVDD voltage to produce controlled output levels. The resistor ratios are specifically designed to limit the voltage across pass gates to safe operating ranges, transforming the extreme voltage levels (0 to AVDD) into moderated levels that protect downstream thin oxide devices.
Solution Approach 2:
The patent introduces intermediate voltage levels through cascaded inverters with controlled threshold voltages. These intermediaries step through multiple voltage stages rather than transitioning directly between extreme levels, preventing overvoltage stress on pass gates and reducing leakage currents during transitions.
2Reliability
If thick oxide FETs are used for higher voltage limits and lower leakage currents, then overvoltage protection and reduced leakage are achieved, but device availability is limited in 14 nm and 10 nm technologies
Solution Approach 1:
The patent changes the operating parameters of thin oxide FETs by controlling the voltage across them through resistor dividers and cascaded inverters. By limiting the voltage swing and maintaining proper voltage levels across pass gates, the circuit enables thin oxide devices to operate reliably in high-voltage environments without requiring thick oxide variants.
Solution Approach 2:
The patent converts the inherent vulnerability of thin oxide FETs to overvoltage into an advantage by designing a control system that actively monitors and limits voltage levels. The cascaded inverter structure with controlled thresholds ensures that thin oxide devices never experience dangerous voltage levels, making the technology node choice irrelevant to voltage handling capability.
3Productivity
If greater voltage difference exists between low level of level shifter and gate of pass gate, then voltage translation range is improved, but higher leakage currents flow between legs of AMUX
Solution Approach 1:
The patent introduces intermediate voltage stages through cascaded inverters that step through multiple controlled levels. Instead of allowing a large voltage difference to exist directly between the level shifter output and pass gate, the intermediate stages break down the voltage transition into smaller steps, maintaining smaller voltage differences across pass gates at all times and thereby reducing leakage currents.
4Device complexity
If indeterminate voltages occur when driving power supply is off or low, then circuit simplicity is maintained, but reliability and predictable operation are compromised
Solution Approach 1:
The patent implements preliminary action by ensuring that the resistor divider network and cascaded inverters are pre-configured to maintain defined voltage levels even when the driving power supply is off or low. The resistor dividers provide predetermined voltage division ratios that establish stable reference levels, and the inverters are designed with threshold voltages that ensure predictable switching behavior under all power supply conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively translates logic signals to output voltage analog levels, preventing overvoltage stress and leakage, ensuring reliable operation even when the source VDD power supply is at 0 volts, and minimizing the chances of overvoltage occurrences in thin oxide devices.
Implementation Method 1
a level shifter resistor divider string of a plurality of series connected resistors, the level shifter resistor divider string connected between an analog voltage rail and an analog ground
Implementation Method 2
A plurality of level shifter cascaded inverters connected between respective resistors of the level shifter resistor divider string and an analog voltage rail and an analog ground
Data Source
AI summary
A method and circuit for implementing a level shifter for translating logic signals to output voltage analog levels, and a design structure on which the subject circuit resides are provided. The circuit includes a level shifter resistor divider string of a plurality of series connected resistors, the level shifter resistor divider string is connected between an analog voltage rail and an analog ground. A plurality of level shifter cascaded inverters are connected between respective resistors of the level shifter resistor divider string and an analog voltage rail and an analog ground. An output of the level shifter is programmed by the level shifter resistor divider string connected to the cascaded inverters.