Cascade MOS Inverter Node Clamping Against Threshold Stress
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Solution Overview
Problem
In semiconductor integrated circuits with multiple transistors connected in series, the non-conducting nodes experience potential differences due to parasitic capacitances, leading to transistor characteristic degradation when a voltage slightly lower than the threshold voltage is applied, causing a high electric field and degrading transistor performance over time.
Innovation Solution
A semiconductor integrated circuit design that includes a voltage application circuit to clamp the node potential when both MOS transistors are non-conducting, preventing characteristic degradation by ensuring the node potential equals the gate potential, thus avoiding the application of a threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If multiple transistors are connected in series to withstand high voltage, then the withstanding voltage capability is improved, but the transistor characteristic degrades due to potential differences on floating nodes
Solution Approach 1:
A third transistor is introduced as an intermediary element connected between the floating node and ground. This intermediary transistor actively manages the potential at the floating node by turning on when the first two transistors are off, preventing harmful potential differences from developing across the series-connected transistors during non-conducting periods.
Solution Approach 2:
The voltage application circuit applies a predetermined voltage to the floating node in advance before the transistors need to conduct again. By pre-establishing the correct potential level on the floating node during the non-conducting period, the circuit prevents threshold voltage application and eliminates the conditions that would lead to transistor characteristic degradation.
2Loss of energy
If transistors are kept in non-conducting state for extended periods, then power consumption is reduced, but transistor characteristic degrades due to high electric field at the drain region
Solution Approach 1:
The third transistor operates periodically in conjunction with the first two transistors. When the first two transistors are in the non-conducting state to save power, the third transistor turns on periodically to reset the floating node potential, preventing the accumulation of harmful electric fields while maintaining overall low power consumption through the periodic rather than continuous operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents transistor characteristic degradation by maintaining the node potential equal to the gate potential during non-conducting periods, thereby inhibiting the deterioration of MOS transistors due to prolonged exposure to a voltage close to the threshold voltage.
Implementation Method 1
there is a possibility that the difference between the potentials on the floating nodes and the gate potential approaches a threshold voltage of the transistors... because of differences in characteristics of the transistors and the influence of a feed-through effect due to parasitic capacitances in the circuit
Data Source
AI summary
A semiconductor integrated circuit capable of maintaining characteristics of transistors in a circuit including a plurality of cascade connected transistors. The circuit includes an inverter which has a series connection of P-MOS transistors and a pair of N-MOS transistors. The P-MOS transistor is connected to a high potential source VH and the N-MOS transistor is connected to a low potential source VL. The gate of each MOS transistor is connected to an input signal line. The inverter circuit further includes a P-MOS transistor connected between a node and input signal line, and an N-MOS transistor connected between a node of the N-MOS transistors and the input signal line. The gates of the P-MOS transistor and the N-MOS transistor are connected to an output signal line of the inverter circuit.