Cascade MOS Transistor Layout for Parasitic Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuits, cascade MOS devices with parallel connections of small MOS devices lead to increased parasitic capacitance and current density in power circuits due to the need for metal lines and contact plugs connecting source/drain regions, limiting the expansion of power buses and frequency response.
Innovation Solution
The formation of cascade MOS devices with virtually connected common source/drain regions eliminates the need for metal connections, allowing power buses to expand and reducing parasitic capacitance by integrating source/drain regions without metal lines and contact plugs, thereby decreasing current density and electro-migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If small MOS devices are connected in parallel to form large MOS devices, then the current carrying capacity is improved, but the parasitic capacitance increases due to metal lines and contact plugs
Solution Approach 1:
The patent merges multiple small MOS devices into a unified large MOS device structure where the source and drain regions are shared across all parallel-connected transistors. This consolidation eliminates the need for separate metal lines and contact plugs for each transistor, thereby maintaining high current carrying capacity while significantly reducing parasitic capacitance.
Solution Approach 2:
The invention extracts and eliminates the unnecessary metal lines and contact plugs from the conventional parallel connection approach. By directly connecting the source and drain regions of parallel MOS devices without intermediate metal interconnects, the harmful parasitic capacitance is removed while preserving the desired current carrying capacity.
2Reliability
If metal lines and contact plugs are used to connect source/drain regions of parallel MOS devices, then electrical connection is achieved, but current density and electro-migration increase
Solution Approach 1:
The patent removes the metal lines and contact plugs from the connection path between parallel MOS devices. By establishing direct semiconductor-to-semiconductor connections between source and drain regions, reliable electrical connection is maintained while eliminating the sources of high current density and electro-migration that plague conventional metal-interconnect approaches.
3Ease of manufacture
If conventional parallel connection with metal interconnects is used, then MOS devices can be connected, but power bus expansion is limited
Solution Approach 1:
The patent merges the source and drain regions of multiple parallel MOS devices into shared regions that serve all transistors simultaneously. This consolidation approach enables power buses to expand freely without being constrained by the need for individual metal connections to each transistor, as the shared source/drain regions provide direct access points for power distribution.
Data Source
AI summary
A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected.