Cascade Multiplier-Accumulator Using Charge Summing Unit Elements
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Solution Overview
Problem
Existing multiplier-accumulator architectures for machine learning applications face high power dissipation due to synchronous clocked operations and increased gate complexity, particularly in scalable hardware designs for multiply-accumulate operations.
Innovation Solution
An asynchronous multiplier-accumulator architecture utilizing AND gates and charge transfer capacitors to minimize internal state changes, with a charge summing unit and analog-to-digital converter to generate digital outputs, allowing for cascaded operations and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous clocked stages are used for multiplication operations, then operational reliability is improved, but power dissipation increases
Solution Approach 1:
The patent transitions from static synchronous clocked operation to dynamic asynchronous operation. The multiplier operates without a global clock, allowing each multiplication operation to proceed at its own pace based on input data arrival, thereby eliminating continuous clock signal power consumption while maintaining operational reliability through handshaking protocols.
Solution Approach 2:
The invention replaces continuous periodic clocking with event-driven periodic action. Multiplication operations are triggered only when input data is ready, using control signals that activate computation only when needed, thus reducing power dissipation compared to continuous synchronous clocking while ensuring reliable operation completion.
2Productivity
If large n×n multiplier architecture is implemented for machine learning applications, then computational capability is improved, but gate complexity increases as n2
Solution Approach 1:
The patent segments the large n×n multiplication problem into multiple smaller k×k unit element multipliers. By dividing the computation into manageable blocks that can be independently computed and then combined, the gate complexity per unit is reduced from O(n²) to O(k²), while the overall computational capability is maintained through parallel or sequential composition of these smaller units.
Solution Approach 2:
The invention introduces a temporal dimension to the multiplication architecture by using asynchronous operation and pipelining. Instead of computing all n² products simultaneously in a single synchronous cycle, the system processes products across multiple time steps, effectively trading spatial complexity for temporal execution, thereby reducing gate complexity while maintaining computational capability.
3Adaptability or versatility
If additional adders are added for multiply-accumulate operations, then computational functionality is improved, but device complexity increases
Solution Approach 1:
The patent merges the multiplication and accumulation operations into a unified circuit structure. The partial products from multiple unit element multipliers are accumulated using shared adder resources rather than dedicated adders for each multiplication, thereby achieving multiply-accumulate functionality while reducing overall device complexity through resource sharing.
Solution Approach 2:
The invention creates universal computation units that can perform both multiplication and accumulation functions. The same circuit components are used for both operations, allowing the system to achieve enhanced computational functionality for machine learning applications without proportionally increasing device complexity, as each unit serves multiple purposes.
4Use of energy by moving object
If internal state changes are minimized for static weighting matrices, then power consumption is reduced, but operational flexibility is constrained
Solution Approach 1:
The patent implements dynamic adaptation of the computation strategy based on input characteristics. When static weighting matrices are detected, the system minimizes internal state changes to reduce power consumption. When dynamic inputs are present, the system automatically increases state changes to maintain operational flexibility, thus resolving the contradiction between power efficiency and adaptability.
Solution Approach 2:
The invention changes operational parameters based on the nature of the computation. For static weighting matrices, parameters are configured to minimize state transitions and power consumption. For dynamic workloads, parameters are adjusted to allow full operational flexibility. This parameter adaptation enables the system to optimize power consumption without permanently constraining operational flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low-power, scalable, and efficient multiply-accumulate operations by minimizing internal state changes and power consumption, particularly when dealing with static weighting matrices in machine learning calculations.
Implementation Method 1
each AND gate output coupled through a capacitor of value Cu to a particular analog charge line of an analog charge bus according to bit order
Implementation Method 2
the analog charge bus coupled to a charge summing unit comprising a plurality of charge summing capacitors which transfer charge according to two to the power of bit order
Implementation Method 3
the charge summing capacitors having a second terminal which are coupled together and coupled to the input of an analog to digital converter (ADC) which provides the product of A and B
Data Source
AI summary
A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.