Cascade Sense Circuit for Parallel Memory Verification
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Solution Overview
Problem
Existing memory devices face challenges in efficiently programming and verifying the conductive state of memory cells, particularly in achieving narrow threshold voltage distributions while minimizing programming time penalties, due to the need for multiple verify operations and sequential application of control gate voltages.
Innovation Solution
A sense circuit is implemented that senses the threshold voltage of a memory cell relative to two different levels using a single control gate voltage, with two sense nodes in a cascade configuration, allowing for the output of first and second bits to indicate the cell's state relative to higher and lower verify voltages, thereby reducing programming time and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple verify operations are performed sequentially with different control gate voltages, then measurement precision of threshold voltage is improved, but loss of time increases
Solution Approach 1:
The patent combines multiple verify operations into a single simultaneous operation by applying multiple control gate voltages at the same time to different memory cells. The sense circuit compares currents from multiple memory cells against multiple reference currents in parallel, allowing simultaneous verification of multiple cells at different threshold voltage levels, thereby reducing total programming time while maintaining verification accuracy
Solution Approach 2:
The patent dynamically adjusts control gate voltages and reference currents based on the programming stage. During programming, control gate voltages are adjusted to match the threshold voltage distribution, and reference currents are dynamically set to correspond to verify voltages. This dynamic adjustment allows the system to adapt to changing conditions and perform multiple verifications efficiently in parallel
2Manufacturing precision
If multiple control gate voltages are applied sequentially, then manufacturing precision of threshold voltage distribution is improved, but productivity decreases
Solution Approach 1:
The patent merges multiple sequential verify operations into a single parallel operation by simultaneously applying multiple control gate voltages to different memory cells and comparing their currents against multiple reference currents. This parallel processing approach maintains the precision needed for narrow threshold voltage distributions while significantly improving programming speed and productivity
Solution Approach 2:
The patent performs preliminary setup of control gate voltages and reference currents before the actual verify operation. Control gate voltages are pre-adjusted to match the threshold voltage distribution, and reference currents are pre-set to correspond to the desired verify voltages. This preliminary action enables the subsequent parallel verify operation to proceed efficiently without sequential delays
Data Source
AI summary
A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be higher and lower verify voltages of a data state in a programming operation, or two read levels of a read operation. Two sense nodes which are connected in a cascade configuration such that a first sense node discharges into the bit line initially, and a second sense node may or may not discharge into the bit line, depending on the level to which the first node has discharged. First and second bits of data can be output from the sense circuit based on the levels of the first and second sense nodes to indicate the threshold voltage of the memory cell relative to the higher and lower verify voltages, respectively.