Cascaded Address Tables for Network Switch Memory
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Solution Overview
Problem
Existing network switches face inefficiencies in routing packets due to large address tables required by new standards like GPON, which increase manufacturing costs and lead to flooding of redundant messages, impacting throughput.
Innovation Solution
Implementing a cascaded address table configuration with separate memory tables connected via electrical lines, allowing sequential searching to efficiently find destination addresses and reduce message flooding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the address table size is increased to satisfy GPON standard requirements, then the switch can provide adequate data throughput and support increased numbers of ports, but the manufacturing cost of the silicon chip increases
Solution Approach 1:
The patent divides a large address table into multiple smaller address tables (first address table, second address table, etc.). Each table stores a portion of the address data, allowing the switch to achieve the required throughput by distributing the storage burden across multiple tables rather than requiring one large table, thereby reducing manufacturing cost.
Solution Approach 2:
The patent introduces a new dimension of organization by arranging multiple address tables in a cascaded hierarchical structure. Instead of a single flat table, the system uses multiple levels of tables where the first table is searched initially, and upon miss, the search cascades to the second table, and so on. This multi-dimensional arrangement allows efficient address lookup while using smaller individual tables.
2Reliability
If relatively large address tables are designed into silicon chips, then the odds of finding an address increase and flooding of ports is avoided, but the cost of manufacturing the silicon chip increases
Solution Approach 1:
The patent segments the address storage function across multiple smaller tables rather than relying on a single large table. The cascaded structure ensures that the combined capacity of all tables provides high odds of finding any address, while each individual table remains small enough to be cost-effective to manufacture.
Solution Approach 2:
The patent combines multiple small address tables into a functional equivalent of a large address table through the cascaded search mechanism. The system merges the storage capacity of several tables while maintaining the reliability of a large table, achieving both cost efficiency and high address finding probability.
3Adaptability or versatility
If the switch floods multiple ports with packets to determine destination, then the switch can learn where destinations reside, but redundant message processing impacts throughput
Solution Approach 1:
The patent implements preliminary action by pre-populating address tables with destination address mappings before flooding is needed. When a packet arrives, the system first searches the cascaded address tables for the destination. Only if the address is not found does the system resort to flooding, thereby reducing redundant message processing and preserving throughput while maintaining the ability to learn new destinations.
Data Source
AI summary
Devices, systems, methods, and other embodiments associated with cascaded memory tables for searching are described. In one embodiment, an integrated chip is implemented with two or more address tables. The two or more address tables are implemented with separate memory tables to store addresses. The two or more address tables are comprised of a first address table and a second address table. Connection lines connect the first address table and the second address table to create a cascaded address table. Search logic initiates a search of the first address table for an address. If the address is not found, the search logic initiates a search of the second address table through the connection lines.